| 項番 | 略 語 | 英 文 ワ ー ド | 日 本 語 ワ ー ド |
| 1 | ALU | Arithmetic and Logical Unit | |
| 2 | ATE | Automatic Test Equipment | |
| 3 | ATPG | Automatic Test Pattern Generator | 自動テストパターン発生 |
| 4 | BALLAST | Balanced structure Scan Test | |
| 5 | BILBO | Built-In Logic Block Observation | |
| 6 | BIOS | Boundary Input/Output Serializer | |
| 7 | BISR | Built-In Self-Repair | |
| 8 | BIST | Built-In Self-Test | 組込自己テスト |
| 9 | BOST | Built-Off Self-Test,Build-Out Self-Test | |
| 10 | BS | Boundary Scan | バウンダリスキャン |
| 11 | BSM | Boundary Scan Master | バウンダリスキャンマスタ |
| 12 | CA | Cellular Automata | セルオートマトン |
| 13 | CAD | Computer Aided Design | コンピュータ利用設計 |
| 14 | CAS | Core Access Switch | |
| 15 | CPU | Central Processor Unit | 中央演算処理装置 |
| 16 | CLB | Configurable Logic Block | |
| 17 | CSTP | Circular Self Test Path | |
| 18 | CUT | Circuit Under Test | 被試験回路 |
| 19 | DBM | Digital Bus monitor | |
| 20 | DFT | Design for Test,Design for Testability | テスト容易化設計 |
| 21 | DSP | Digital Signal Processor | |
| 22 | DSRL | Delay Shift Register Lacth | |
| 23 | DTL | Dynamic Termination Logic | |
| 24 | DUT | Device Under Test | 被試験装置 |
| 25 | EDA | Electronic Design Automation | コンピュータ利用設計 |
| 26 | FPGA | Field Programmable Gate Array | |
| 27 | FSM | Finite State Machine | 有限状態機械 |
| 28 | HIST | Hierarchical Self Test | |
| 29 | IDDQ | Quiescent Supply Current | |
| 30 | IEEE-1149.1 | Test Access Port & Boundary Scan Architecture | バウンダリスキャン用規格 |
| 31 | IEEE-P1500 | Embedded Core Test Inteface(Draft Standard) | コアテスト用規格 |
| 32 | ILA | Iterative Logic Array | |
| 33 | JTAG | Joint Test Action Group | |
| 34 | LBIST | Logic Built In Self Test | |
| 35 | LFSR | Linear Feedback Shift Register | 線形帰還シフトレジスタ |
| 36 | LSSD | Level Sensitive Scan Design | |
| 37 | MAC | Medium Access controller | |
| 38 | MBIST | Memory Built In Self Test | メモリ用BIST |
| 39 | MCM | Multi-Chip Modules | |
| 40 | MISA | Multi-input Signature Analyzer | 並列入力シグネチャ解析器 |
| 41 | MISR | Multiple Input Signature Register | 並列入力シグネチャ解析器 |
| 42 | MSME | Multi-Mode Scannable Memory Element | |
| 43 | MUX | Multiplexer | マルチプレクサ |
| 44 | ODA | Output Data Analyzer | |
| 45 | ORA | Output Response Analyzer | |
| 46 | PLA | Programmable Logic Array | |
| 47 | PLD | Programmable Logic Device | |
| 48 | PRPG | Pseudo Random Pattern Generator | 擬似乱数発生器 |
| 49 | RAM | Random Access Memory | |
| 50 | RISC | Reduced Instruction Set Computer | 縮小命令セット計算機 |
| 51 | ROM | Read Only Memory | |
| 52 | RPR | Random Pattern Resistant | ランダムパターン抵抗性 |
| 53 | RTL | Register Transfer Language | |
| 54 | SOC | System On a Chip | |
| 55 | SRL | Shift Register Latch | |
| 56 | SRSG | Shift Register Sequence Generator | |
| 57 | STMCS | Scan Test for Multi Clock System | |
| 58 | STS | Selectively Transparent Scan | |
| 59 | STUMPS | Self-Test Using MISR and parallel SRSG | |
| 60 | TAP | Test Access Port | テストアクセスポート |
| 61 | TAM | Test Access Mechanism | |
| 62 | TGC | Test Generator Circuits | |
| 63 | TPG | Test Pattern Generator | テストパターン発生器 |
| 64 | UDL | User Defined Logic. | ユーザー定義回路 |
| 65 | WDF | Wave Digital Filter | |
| 66 | WSR | Wrapper Scan Register | |
| 67 | WRP | Weighted Random Pattern | |