H10B10/00	7	Static random access memory [SRAM] devices	H10B10/00	H10B10/00		2740
H10B10/10	8	SRAM devices comprising bipolar components	H10B10/10	H10B10/10		291
H10B10/12	8	{comprising a MOSFET load element}	H10B10/00	H10B10/12		3294
H10B10/125	9	{the MOSFET being a thin film transistor [TFT]}	H10B10/00	H10B10/125		1152
H10B10/15	8	{comprising a resistor load element}	H10B10/00	H10B10/15		585
H10B10/18	8	{Peripheral circuit regions}	H10B10/00	H10B10/18		848
H10B12/00	7	Dynamic random access memory [DRAM] devices	H10B12/00	H10B12/00		5032
H10B12/01	8	{Manufacture or treatment}	H10B12/00	H10B12/01		1375
H10B12/02	9	{for one transistor one-capacitor [1T-1C] memory cells}	H10B12/00	H10B12/02		1210
H10B12/03	10	{Making the capacitor or connections thereto}	H10B12/00	H10B12/03		2251
H10B12/033	11	{the capacitor extending over the transistor}	H10B12/00	H10B12/033		4906
H10B12/0335	12	{Making a connection between the transistor and the capacitor, e.g. plug}	H10B12/00	H10B12/0335		5374
H10B12/036	11	{the capacitor extending under the transistor}	H10B12/00	H10B12/036		314
H10B12/038	11	{the capacitor being in a trench in the substrate}	H10B12/00	H10B12/038		1124
H10B12/0383	12	{wherein the transistor is vertical}	H10B12/00	H10B12/0383		553
H10B12/0385	12	{Making a connection between the transistor and the capacitor, e.g. buried strap}	H10B12/00	H10B12/0385		567
H10B12/0387	12	{Making the trench}	H10B12/00	H10B12/0387		887
H10B12/05	10	{Making the transistor}	H10B12/00	H10B12/05		3257
H10B12/053	11	{the transistor being at least partially in a trench in the substrate (vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383)}	H10B12/00	H10B12/053		2938
H10B12/056	11	{the transistor being a FinFET}	H10B12/00	H10B12/056		458
H10B12/09	9	{with simultaneous manufacture of the peripheral circuit region and memory cells}	H10B12/00	H10B12/09		3517
H10B12/10	8	DRAM devices comprising bipolar components	H10B12/10	H10B12/10		153
H10B12/20	8	{DRAM devices comprising floating-body transistors, e.g. floating-body cells}	H10B12/00	H10B12/20		929
H10B12/30	8	{DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells}	H10B12/00	H10B12/30		4252
H10B12/31	9	{having a storage electrode stacked over the transistor}	H10B12/00	H10B12/31		2011
H10B12/312	10	{with a bit line higher than the capacitor}	H10B12/00	H10B12/312		436
H10B12/315	10	{with the capacitor higher than a bit line}	H10B12/00	H10B12/315		3628
H10B12/318	10	{the storage electrode having multiple segments}	H10B12/00	H10B12/318		1221
H10B12/33	9	{the capacitor extending under the transistor}	H10B12/00	H10B12/33		418
H10B12/34	9	{the transistor being at least partially in a trench in the substrate}	H10B12/00	H10B12/34		2191
H10B12/36	9	{the transistor being a FinFET}	H10B12/00	H10B12/36		522
H10B12/37	9	{the capacitor being at least partially in a trench in the substrate}	H10B12/00	H10B12/37		1327
H10B12/373	10	{the capacitor extending under or around the transistor}	H10B12/00	H10B12/373		279
H10B12/377	10	{having a storage electrode extension located over the transistor}	H10B12/00	H10B12/377		167
H10B12/39	9	{the capacitor and the transistor being in a same trench}	H10B12/00	H10B12/39		99
H10B12/395	10	{the transistor being vertical}	H10B12/00	H10B12/395		639
H10B12/48	9	{Data lines or contacts therefor}	H10B12/00	H10B12/48		848
H10B12/482	10	{Bit lines}	H10B12/00	H10B12/482		5483
H10B12/485	10	{Bit line contacts}	H10B12/00	H10B12/485		3468
H10B12/488	10	{Word lines}	H10B12/00	H10B12/488		3074
H10B12/50	8	{Peripheral circuit region structures}	H10B12/00	H10B12/50		2919
H10B20/00	7	Read-only memory [ROM] devices	H10B20/00	H10B20/00		1719
H10B20/10	8	ROM devices comprising bipolar components	H10B20/10	H10B20/10		137
H10B20/20	8	Programmable ROM [PROM] devices comprising field-effect components (H10B20/10 takes precedence)	H10B20/20	H10B20/20		401
H10B20/25	9	One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links	H10B20/25	H10B20/25		1105
H10B20/27	8	{ROM only}	H10B20/00	H10B20/27		59
H10B20/30	9	{having the source region and the drain region on the same level, e.g. lateral transistors}	H10B20/00	H10B20/30		69
H10B20/34	10	{Source electrode or drain electrode programmed}	H10B20/00	H10B20/34		140
H10B20/36	10	{Gate programmed, e.g. different gate material or no gate}	H10B20/00	H10B20/36		47
H10B20/363	11	{Gate conductor programmed}	H10B20/00	H10B20/363		30
H10B20/367	11	{Gate dielectric programmed, e.g. different thickness}	H10B20/00	H10B20/367		58
H10B20/38	10	{Doping programmed, e.g. mask ROM}	H10B20/00	H10B20/38		306
H10B20/383	11	{Channel doping programmed}	H10B20/00	H10B20/383		289
H10B20/387	11	{Source region or drain region doping programmed}	H10B20/00	H10B20/387		107
H10B20/40	9	{having the source region and drain region on different levels, e.g. vertical channel}	H10B20/00	H10B20/40		87
H10B20/50	9	{having transistors on different levels, e.g. 3D ROM}	H10B20/00	H10B20/50		73
H10B20/60	8	{Peripheral circuit regions}	H10B20/00	H10B20/60		127
H10B20/65	9	{of memory structures of the ROM only type}	H10B20/00	H10B20/65		126
H10B41/00	7	Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates	H10B41/00	H10B41/00		1473
H10B41/10	8	characterised by the top-view layout	H10B41/10	H10B41/10		3413
H10B41/20	8	characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels	H10B41/20	H10B41/20		2283
H10B41/23	9	with source and drain on different levels, e.g. with sloping channels	H10B41/23	H10B41/23		153
H10B41/27	10	the channels comprising vertical portions, e.g. U-shaped channels	H10B41/27	H10B41/27		6370
H10B41/30	8	characterised by the memory core region	H10B41/30	H10B41/30		8769
H10B41/35	9	with a cell select transistor, e.g. NAND	H10B41/35	H10B41/35		6094
H10B41/40	8	characterised by the peripheral circuit region	H10B41/40	H10B41/40		3419
H10B41/41	9	of a memory region comprising a cell select transistor, e.g. NAND	H10B41/41	H10B41/41		2214
H10B41/42	9	Simultaneous manufacture of periphery and memory cells	H10B41/42	H10B41/42		918
H10B41/43	10	comprising only one type of peripheral transistor	H10B41/43	H10B41/43		266
H10B41/44	11	with a control gate layer also being used as part of the peripheral transistor	H10B41/44	H10B41/44		301
H10B41/46	11	with an inter-gate dielectric layer also being used as part of the peripheral transistor	H10B41/46	H10B41/46		167
H10B41/47	11	with a floating-gate layer also being used as part of the peripheral transistor	H10B41/47	H10B41/47		209
H10B41/48	11	with a tunnel dielectric layer also being used as part of the peripheral transistor	H10B41/48	H10B41/48		366
H10B41/49	10	comprising different types of peripheral transistor	H10B41/49	H10B41/49		794
H10B41/50	8	characterised by the boundary region between the core region and the peripheral circuit region	H10B41/50	H10B41/50		1936
H10B41/60	8	the control gate being a doped region, e.g. single-poly memory cell	H10B41/60	H10B41/60		533
H10B41/70	8	the floating gate being an electrode shared by two or more components	H10B41/70	H10B41/70		667
H10B43/00	7	EEPROM devices comprising charge-trapping gate insulators	H10B43/00	H10B43/00		509
H10B43/10	8	characterised by the top-view layout	H10B43/10	H10B43/10		4751
H10B43/20	8	characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels	H10B43/20	H10B43/20		3130
H10B43/23	9	with source and drain on different levels, e.g. with sloping channels	H10B43/23	H10B43/23		124
H10B43/27	10	the channels comprising vertical portions, e.g. U-shaped channels	H10B43/27	H10B43/27		10603
H10B43/30	8	characterised by the memory core region	H10B43/30	H10B43/30		4287
H10B43/35	9	with cell select transistors, e.g. NAND	H10B43/35	H10B43/35		6542
H10B43/40	8	characterised by the peripheral circuit region	H10B43/40	H10B43/40		4866
H10B43/50	8	characterised by the boundary region between the core and peripheral circuit regions	H10B43/50	H10B43/50		4188
H10B51/00	7	Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors	H10B51/00	H10B51/00		376
H10B51/10	8	characterised by the top-view layout	H10B51/10	H10B51/10		476
H10B51/20	8	characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels	H10B51/20	H10B51/20		955
H10B51/30	8	characterised by the memory core region	H10B51/30	H10B51/30		1486
H10B51/40	8	characterised by the peripheral circuit region	H10B51/40	H10B51/40		243
H10B51/50	8	characterised by the boundary region between the core and peripheral circuit regions	H10B51/50	H10B51/50		159
H10B53/00	7	Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors	H10B53/00	H10B53/00		2272
H10B53/10	8	characterised by the top-view layout	H10B53/10	H10B53/10		197
H10B53/20	8	characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels	H10B53/20	H10B53/20		548
H10B53/30	8	characterised by the memory core region	H10B53/30	H10B53/30		2548
H10B53/40	8	characterised by the peripheral circuit region	H10B53/40	H10B53/40		363
H10B53/50	8	characterised by the boundary region between the core and peripheral circuit regions	H10B53/50	H10B53/50		113
H10B61/00	7	Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices	H10B61/00	H10B61/00		3928
H10B61/10	8	{comprising components having two electrodes, e.g. diodes or MIM elements}	H10B61/00	H10B61/10		908
H10B61/20	8	{comprising components having three or more electrodes, e.g. transistors}	H10B61/00	H10B61/20		528
H10B61/22	9	{of the field-effect transistor [FET] type}	H10B61/00	H10B61/22		3302
H10B63/00	7	Resistance change memory devices, e.g. resistive RAM [ReRAM] devices	H10B63/00	H10B63/00		922
H10B63/10	8	Phase change RAM [PCRAM, PRAM] devices	H10B63/10	H10B63/10		1077
H10B63/20	8	{comprising selection components having two electrodes, e.g. diodes}	H10B63/00	H10B63/20		2228
H10B63/22	9	{of the metal-insulator-metal type}	H10B63/00	H10B63/22		341
H10B63/24	9	{of the Ovonic threshold switching type}	H10B63/00	H10B63/24		867
H10B63/30	8	{comprising selection components having three or more electrodes, e.g. transistors}	H10B63/00	H10B63/30		3014
H10B63/32	9	{of the bipolar type}	H10B63/00	H10B63/32		204
H10B63/34	9	{of the vertical channel field-effect transistor type}	H10B63/00	H10B63/34		890
H10B63/80	8	{Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays}	H10B63/00	H10B63/80		3609
H10B63/82	9	{the switching components having a common active material layer}	H10B63/00	H10B63/82		561
H10B63/84	9	{arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays}	H10B63/00	H10B63/84		2102
H10B63/845	10	{the switching components being connected to a common vertical conductor}	H10B63/00	H10B63/845		1093
H10B69/00	7	Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices	H10B69/00	H10B69/00		7533
H10B80/00	7	Assemblies of multiple devices comprising at least one memory device covered by this subclass<br><br><u>WARNING</u><br>Group H10B80/00 is incomplete pending reclassification of documents from group H10W90/00. <br>Groups H10W90/00 and H10B80/00 should be considered in order to perform a complete search.	H10B80/00	H10B80/00		2581
H10B99/00	7	Subject matter not provided for in other groups of this subclass	H10B99/00	H10B99/00		1115
H10B99/10	8	{Memory cells having a cross-point geometry}	H10B99/00	H10B99/10		135
H10B99/14	8	{comprising memory cells that only have passive resistors or passive capacitors}	H10B99/00	H10B99/14		32
H10B99/16	8	{comprising memory cells having diodes}	H10B99/00	H10B99/16		74
H10B99/20	8	{comprising memory cells having thyristors}	H10B99/00	H10B99/20		60
H10B99/22	8	{including field-effect components}	H10B99/00	H10B99/22		273
