G11C   5/00  \	0	0	5L105	G11C   5/00	2985	ǣãʬव뵭֤κ	Details of stores covered by group G11C 11/00
G11C   5/00 100 \	1	1	5L105	G11C   5/00	200	ȾƳε֤ξξüФݸϩͤˤܥСɤѤȾƳΤ¤Σȣ̣긡Сƻǣƣ	Protection circuits against loss of information of semiconductor storage devices (manufacturing semi-conductor by using bombardment with radiation H01L21/26; error detection, monitoring G06F11/00)
G11C   5/02  \	1	1	5B073	G11C   5/02	42	ǻҤ֡㡥ޥȥåˤ	Disposition of storage elements, e.g. in the form of a matrix array
G11C   5/02 100 \	2	2	5L105	G11C   5/02	3737	ȾƳε֤ˤꥻ뤪ӼղϩδŪ쥤ȡʽѲϩˤʤδŪ쥤ȣȣ̣	Geometric layout of memory cells and peripheral circuits in a semiconductor storage device (geometrical layout of the components in integrated circuits, H01L27/02)
G11C   5/04  \	2	2	5B073	G11C   5/04	82	ǻҤΤλٻΡΤ褦ʻٻΤؤεϿǻҤμդޤϸ	Supports for storage elements; Mounting or fixing of storage elements on such supports
G11C   5/04 200 \	3	3	5L105	G11C   5/04	1395	⥸塼	Memory module
G11C   5/04 210 \	4	4	5L105	G11C   5/04	761	ңϣͥ⥸塼	ROM module
G11C   5/04 220 \	4	4	5L105	G11C   5/04	1213	ңͥ⥸塼	RAM module
G11C   5/05  \	3	3	5B073	G11C   5/05	19	ޥȥå˻ٻΡΣ	Supporting of cores in matrix [2]
G11C   5/06  \	1	1	5B073	G11C   5/06	32	ǻҤŵŪ߷礹뵡㡥磻	Arrangements for interconnecting storage elements electrically, e.g. by wiring
G11C   5/06 100 \	2	2	5L105	G11C   5/06	133	ȾƳΥꥢ㡥ӥåˤŰӿʬۡٱк	Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-lines, bit-lines, propagation delay countermeasures
G11C   5/06 200 \	2	2	5L105	G11C   5/06	195	ȾƳΥꥯåѳ︺뤿μʡ㡥ʤȤ⥢ɥ쥹ӥǡ¿Ųˤ	Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least addresses and data signals
G11C   5/08  \	2	2	5B073	G11C   5/08	10	ŪǻҤ߷礹뤿ΤΡ㡥ȥ뼧Ф	for interconnecting magnetic elements, e.g. toroidal cores
G11C   5/10  \	2	2	5B073	G11C   5/10	0	ǥ󥵤߷礹뤿Τ	for interconnecting capacitors
G11C   5/12  \	1	1	5B073	G11C   5/12	38	ǻҤ߷礹뤿Ѥ֤ޤˡ㡥̤Τ	Apparatus or processes for interconnecting storage elements, e.g. for threading magnetic cores
G11C   5/14  \	1	1	5L105	G11C   5/14	5592	϶֡Σ	Power supply arrangements [2006.01]
G11C   5/14 100 \	2	2	5L105	G11C   5/14	1555	ХåƥꤪӥХååŸʥХååŸΤΣȣʣ	Battery and back-up supplies (back-up supplies per se H02J9/06)
G11C   5/14 200 \	2	2	5L105	G11C   5/14	138	̵Ÿ㡥̵żͶƳֳʰ̣ȣʣ	Contactless power supplies, e.g. radio, electromagnetic induction, infrared ray radiation (in general H02J5/00)
G11C   5/14 300 \	2	2	5L105	G11C   5/14	425	ꥫåФθСŸӥƳ̥åŸưǡ٥θСŸ֤ؤʣǣãͥ	Detection of memory cassette insertion/removal; Continuity checks of supply and ground lines; Detection of supply variations/interruptions/levels; Switching between alternative supplies (G11C5/14, 100 takes precedence)
G11C   5/14 320 \	3	3	5L105	G11C   5/14	63	϶ͽꤵ줿Ǥޤ㲼θ	Detection of predetermined disconnection or reduction of power supply
G11C   5/14 370 \	2	2	5L105	G11C   5/14	977		Power saving
G11C   5/14 400 \	2	2	5L105	G11C   5/14	1954	㡼ݥפαѡŰϩΤΥײϩʣǣãͥ	Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor (G11C5/14, 100 takes precedence)
G11C   5/14 420 \	3	3	5L105	G11C   5/14	965	ĥХȯʣǣãͥ	Substrate bias generators (G11C5/14, 100 takes precedence)
G11C   5/14 500 \	2	2	5L105	G11C   5/14	1212	ŰȯŰήĴ㲼Ÿ٥롨Ű㲼Фʣǣãͥ	Voltage reference generators, voltage and current regulators; Internally lowered supply level; Compensation for voltage drops (G11C5/14, 100 takes precedence)
G11C   5/14 550 \	2	2	5L105	G11C   5/14	75	ޤϹ߰ϩХϩޤϩκ	Details of power up or power down circuits, standby circuits or recovery circuits
G11C   7/00  \	0	0	5B094	G11C   7/00	2288	ǥ뵭֤˾񤭹ߤޤϥǥ뵭֤ɤ߽Фʣǣãͥ表ȾƳ֤ѤΤμյϩǣãǣãǣãˡΣ	Arrangements for writing information into, or reading information out from, a digital store (G11C 5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C 11/4063, G11C 11/413, G11C 11/4193) [2,5]
G11C   7/02  \	1	1	5B094	G11C   7/02	11	򤹤ʤĤ	with means for avoiding parasitic signals
G11C   7/04  \	1	1	5B094	G11C   7/04	357	٤αƶ˴Ť㳲ʤĤ	with means for avoiding disturbances due to temperature effects
G11C   7/06  \	1	1	5B094	G11C   7/06	1684	ϢϩΣ	Sense amplifiers; Associated circuits [2006.01]
G11C   7/06 110 \	2	2	5B094	G11C   7/06	452	ݻư㡥ѥ졼󥰥ơ	Differential amplifiers of non-latching type, e.g. comparators, long-tailed pairs
G11C   7/06 120 \	2	2	5B094	G11C   7/06	657	ݻư	Differential amplifiers of latching type
G11C   7/06 130 \	2	2	5B094	G11C   7/06	344	󥰥륨	Single-ended amplifiers
G11C   7/08  \	2	2	5B094	G11C   7/08	123	Σ	Control thereof [7]
G11C   7/10  \	1	1	5B094	G11C   7/10	3280	ϡϡʣɡϡ˥ǡ󥿡ե֡㡥ɡϥǡϩɡϥǡХåեΣ	Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers [2006.01]
G11C   7/10 100 \	2	2	5B094	G11C   7/10	82	ǥޤϥ󥰥Х굡ΤΥ󥿡եϩ	Interface circuits for daisy chain or ring bus memory arrangements
G11C   7/10 150 \	2	2	5B094	G11C   7/10	1727	ǡ㡥ߤޤɽФΥǡΡǡХåޤϤΤϩ	Data management, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
G11C   7/10 152 \	3	3	5B094	G11C   7/10	77	ϻΥǡޥ	Data masking during input/output
G11C   7/10 154 \	3	3	5B094	G11C   7/10	34	ϻΥǡ¤Ӵ㡥Сޥץ쥯ν³³եȤޤϥơ	Data reordering during input/output, e.g. crossbars, cascade arrangement of multiplexers, shifting or rotation
G11C   7/10 200 \	2	2	5B094	G11C   7/10	0	ñݡȥɼݽߥ⡼ɡʤݡȤޤϥꥢݡȤΤ줫ͭ	Read-write modes for single port memories, i.e. having either a random port or a serial port
G11C   7/10 210 \	3	3	5B094	G11C   7/10	683	ꥢӥå⡼ɡ㡥ӥåɥ쥹եȥ쥸ӥåɥ쥹󥿡ӥåСȥ󥿤Ѥ	Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
G11C   7/10 212 \	4	4	5B094	G11C   7/10	429	ڡꥢӥå⡼ɡʤϢɥ쥹ȼѲǽɥ쥹ȥѥ륹Ӥ줾줬Ϣӥåɥ쥹ȼѲǽॢɥ쥹ȥѥ륹Ѥ	Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of usable column address stroke pulses each with its associated bit line address
G11C   7/10 214 \	4	4	5B094	G11C   7/10	39	Ĺǡϡʣţģϡ˥⡼ɡʤĹ֤ˤ錄ϥХåեѲǽ֤˰ݻ	Extended data output [EDO] mode, i.e. keeping output buffer usable during an extended period of time
G11C   7/10 216 \	4	4	5B094	G11C   7/10	109	Ūǥɥꥢӥå⡼ɡʤϢɥ쥹ȼѲǽɥ쥹ȥѥ륹ӻѲǽӥåɥ쥹Ѥ	Static column decode serial bit line access mode, i.e. using a usable row address stroke pulse with its associated word line address and a sequence of usable bit line addresses
G11C   7/10 220 \	3	3	5B094	G11C   7/10	1	ľ˥ɥ쥹ꤵ줿ɼݽߥǡ쥸ѤΡʣǣãͥ	using serially addressed read-write data registers (G11C7/10, 230 takes precedence)
G11C   7/10 226 \	4	4	5B094	G11C   7/10	122	ʳϢ³Ū˥ǡϤ뤿ˣĤʳΤߤ򥢥ɥ쥹ꤹǡ쥸ѤΡ㡥˥֥ɼݽߥ⡼	using data registers of which only one stage is addressed for sequentially outputting data from a predetermined number of stages, e.g. nibble read-write mode
G11C   7/10 230 \	3	3	5B094	G11C   7/10	347	ǡեȥ쥸Ѥ	using data shift registers
G11C   7/10 240 \	3	3	5B094	G11C   7/10	557	ѥץ饤󵻽ѤѤΡʤǽ֤ΥåѤΡ㡥ǥɡϥХåե	using pipelining techniques, i.e. using latches between functional parts, e.g. row/column decoders, I/O buffers, sense amplifiers
G11C   7/10 250 \	3	3	5B094	G11C   7/10	47	󥿥꡼ֵѤѤΡʤΣĤʬ֤˼»ܤ̤ʬɼݽ	using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
G11C   7/10 260 \	3	3	5B094	G11C   7/10	5	ɼݽߥ⡼ϩ	Read-write mode selection circuits
G11C   7/10 300 \	2	2	5B094	G11C   7/10	807	ǡХϩ㡥ץ㡼ץꥻåȡ	Data bus control circuits, e.g. precharging, presetting, equalizing
G11C   7/10 400 \	2	2	5B094	G11C   7/10	220	ǡϲϩ㡥ɽФǡϥХåեǡϥ쥸ǡϥ٥Ѵϩ	Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
G11C   7/10 405 \	3	3	5B094	G11C   7/10	1729	ǡϥХåե㡥٥ѴϩŬŪɲϩޤ	Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
G11C   7/10 415 \	3	3	5B094	G11C   7/10	116	ǡϥå	Data output latches
G11C   7/10 420 \	3	3	5B094	G11C   7/10	23	濮νϲϩ㡥ơޤϥӥե饰ޥɿΥեɥХå	Control signal output circuits, e.g. status or busy flags, feedback of command signals
G11C   7/10 425 \	3	3	5B094	G11C   7/10	7	ϤƱ	Output synchronization
G11C   7/10 450 \	3	3	5B094	G11C   7/10	188	ɣɤ߽Ф	I/O lines read out arrangements
G11C   7/10 455 \	2	2	5B094	G11C   7/10	3002	åѥ륹ƱॢݡȤͭѤΤΡ㡥Ʊꡤʥߥ󥰹碌	for memories with random access ports synchronized on clock signal pulse trains, e.g. synchronous memories, self timed memories
G11C   7/10 460 \	3	3	5B094	G11C   7/10	917	ģģ	DDR
G11C   7/10 480 \	2	2	5B094	G11C   7/10	2601	줾줬ॢݡȤȥꥢݡȤȤͭ¿ݡȥѤΤΡ㡥ӥǥң	for multiport memories each having random access ports and serial ports, e.g. video RAM
G11C   7/10 500 \	2	2	5B094	G11C   7/10	26	ǡϲϩ㡥ǡϥХåեǡϥ쥸ǡϥ٥Ѵϩ	Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
G11C   7/10 505 \	3	3	5B094	G11C   7/10	769	ǡϥХåե㡥٥ѴϩŬŪɲϩޤ	Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
G11C   7/10 510 \	3	3	5B094	G11C   7/10	66	ǡϥå	Data input latches
G11C   7/10 515 \	3	3	5B094	G11C   7/10	611	濮ϲϩ	Control signal input circuits
G11C   7/10 520 \	3	3	5B094	G11C   7/10	8	ϤƱ	Input synchronization
G11C   7/10 525 \	3	3	5B094	G11C   7/10	246	񤭹߲ϩ㡥ɣΥ饤ȥɥ饤	Write circuits, e.g. I/O line write drivers
G11C   7/12  \	1	1	5B094	G11C   7/12	2500	ӥåϩ㡥ӥåѤΡɥ饤С֡ץ륢åײϩץϩץ㡼󥰲ϩϩΣ	Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalizing circuits, for bit lines [7]
G11C   7/14  \	1	1	5B094	G11C   7/14	1290	ߡѥեŰȯϩΣ	Dummy cell management; Sense reference voltage generating circuits [7]
G11C   7/16  \	1	1	5B094	G11C   7/16	209	ʥǥʣġѴǥꡤӥǥ롿ʥʣġѴ狼֤Ȥäǥ뵭֤ؤΥʥεΣ	Storage of analogue signals in digital storage using an arrangement comprising analogue/digital (A/D) converters, digital memories and digital/analogue (D/A) converters [7]
G11C   7/18  \	1	1	5B094	G11C   7/18	1166	ӥåӥå֡Σ	Bit line organization; Bit line layout [7]
G11C   7/20  \	1	1	5B094	G11C   7/20	1400	ꥻϩ㡥ѥåפȤޤϥѥ󤷤ȤΡꡦꥢߥ᡼Σ	Memory cell initialization circuits, e.g. when powering up or down, memory clear, latent image memory [7]
G11C   7/22  \	1	1	5B094	G11C   7/22	389	ɽФݽߡΣҡݣסϤΥߥ󥰡ޤϥåϩɽФݽߡΣҡݣס濮ȯޤϴΣ	Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management [7]
G11C   7/22 100 \	2	2	5B094	G11C   7/22	2695	ΥåϩåƱϩåʬ۲ϩ	Clock generating, synchronizing or distributing circuits within memory devices
G11C   7/22 200 \	2	2	5B094	G11C   7/22	15	åϥХåե	Clock input buffers
G11C   7/22 300 \	2	2	5B094	G11C   7/22	555	ߡǻҤޤϥץꥫϩ˴ŤΥߥ	Timing of memory operations based on dummy memory elements or replica circuits
G11C   7/24  \	1	1	5B094	G11C   7/24	278	ꡦΰϩޤݸϩ㡥դɽФޤϽߤɤ֡ơ롨ƥȡΣ	Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells [7]
G11C   8/00  \	0	0	5B094	G11C   8/00	588	ǥ뵭֤Υɥ쥹򤹤뵡ʣǣãǣãͥ表ȾƳ֤Ѥ֤ΤβϩǣãǣãǣãˡΣ	Arrangements for selecting an address in a digital store (G11C11/00 to G11/C17/00 take precedence; circuits for stores using semiconductor devices G11C 11/4063, G11C 11/413, G11C 11/4193) [2,5]
G11C   8/02  \	1	1	5B094	G11C   8/02	102	ޥȥåѤΡΣ	using selecting matrix [2]
G11C   8/04  \	1	1	5B094	G11C   8/04	349	缡ɥ쥷֤ѤΡ㡥եȥ쥸󥿡Σ	using a sequential addressing device, e.g. shift register, counter [2006.01]
G11C   8/06  \	1	1	5B094	G11C   8/06	16	ɥ쥹󥿡ե֡㡥ɥ쥹ХåեΣ	Address interface arrangements, e.g. address buffers [2006.01]
G11C   8/06 100 \	2	2	5B094	G11C   8/06	291	ɥ쥹Хåե	Address buffers
G11C   8/08  \	1	1	5B094	G11C   8/08	622	ϩ㡥ѤΥɥ饤С֡ץ륢åײϩץϩץ㡼ϩΣ	Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines [7]
G11C   8/10  \	1	1	5B094	G11C   8/10	951	ǥΣ	Decoders [7]
G11C   8/12  \	1	1	5B094	G11C   8/12	41	롼ϩ㡥֥å򡤥å򡤥쥤ѤΡΣ	Group selection circuits, e.g. for memory block selection, chip selection, array selection [7]
G11C   8/12 200 \	2	2	5B094	G11C   8/12	321	åϩ	Chip selection circuits
G11C   8/14  \	1	1	5B094	G11C   8/14	121	ɥ饤ɥ饤֡Σ	Word line organization; Word line layout [7]
G11C   8/16  \	1	1	5B094	G11C   8/16	999	ޥꡦ쥤㡥ʤȤĤΩɥ쥹饤󡦥롼פˤäơĤεǻҤ򥢥ɥ쥹򤹤ΡΣ	Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups [7]
G11C   8/18  \	1	1	5B094	G11C   8/18	9	ɥ쥹ߥ󥰡ޤϥåϩɥ쥹濮ȯޤϴ㡥ɥ쥹ȥֿޤϥॢɥ쥹ȥֿΤΤΡΣ	Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals [7]
G11C   8/20  \	1	1	5B094	G11C   8/20	46	ɥ쥹ϩޤݸϩʤޤϸäɻߤ֡Σ	Address safety or protection circuits, i.e. arrangements for preventing unauthorized or accidental access [7]
G11C  11/00  \	0	0	5B073	G11C  11/00	44	ŵŪޤϼŪǻҤλѤˤäħŤ줿ǥ뵭֡ΤεǻҡʣǣãǣãͥˡΣ	Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor (G11C 14/00-G11C 21/00 take precedence);;
G11C  11/00 100 \	1	1	5B094	G11C  11/00	94	礵ƤϤ뤬Ωưң͡ݣңϣ͡ң͡ݣУңϣ͡ң͡ݣţУңϣͥ뤫	comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
G11C  11/02  \	1	1	5B073	G11C  11/02	1247	ŪǻҤѤ	using magnetic elements
G11C  11/04  \	2	2	5B073	G11C  11/04	2	εǻҡ㡥åɡ磻ѤΡʣǣãǣãͥˡΣ	using storage elements having cylindrical form, e.g. rod, wire (G11C 11/12, G11C 11/14 take precedence) [2]
G11C  11/06  \	2	2	5B073	G11C  11/06	36	ñ쵭ǻҤѤΡ㡥ȥ뼧¿ĤѤ줾ιĤεǻҤ	using single-aperture storage elements, e.g. ring core; using multi-aperture plates in which each individual aperture forms a storage element
G11C  11/061  \	3	3	5B073	G11C  11/061	1	ǻҤǣӥåȤ򵭲˲ɽФԤʤñιޤϼ롼פͭǻҤѤΡΣ	using elements with single aperture or magnetic loop for storage of one element per bit, and for destructive read-out [2]
G11C  11/063  \	4	4	5B073	G11C  11/063	0	̡ġĥ˥Τ褦˥ӥåȤȿ줿ΡʤߤɽФˤ꾯ʤȤ⣲Ĥΰפήˤ꣱ĤεǻҤ򤹤뤿ȿ줿ΡΣ	bit-organised, such as 2L/2D-organisation or three-dimensional [3D]-organisation, i.e. for selection of an element by means of at least two coincident partial currents both for reading and for writing[2006.01]
G11C  11/065  \	4	4	5B073	G11C  11/065	1	ĥ˥ޤϥ˥Τ褦˥ɤȿ줿ΡʤñȤνʬɽФήˤ꣱ʬǻҤ򤹤뤿ȿ줿ΡΣ	word-organised, such as two-dimensional [2D]-organisation, or linear selection, i.e. for selection of all the elements of a word by means of a single full current for reading[2006.01]
G11C  11/067  \	3	3	5B073	G11C  11/067	12	ǻҤǣӥåȤ򵭲˲ɽФԤʤñιޤϼ롼פͭǻҤѤΡΣ	using elements with single aperture or magnetic loop for storage of one element per bit, and for non-destructive read-out [2]
G11C  11/08  \	2	2	5B073	G11C  11/08	95	¿ǻҤѤΡ㡥ȥ󥹥ե饯ѤΡʣĤΩ¿ǻҤȤ߹ľΤѤΡʣǣãͥˡΣ	using multi-aperture storage elements, e.g. using transfluxors; using plates incorporating several individual multi-aperture storage elements (G11C 11/10 takes precedence) [2006.01]
G11C  11/10  \	2	2	5B073	G11C  11/10	0	¿ǻҤѤ	using multi-axial storage elements
G11C  11/12  \	2	2	5B073	G11C  11/12	1	ƥ󥵡ѤΡȥѤΡʤμͤƤ	using tensors; using twistors, i.e. elements in which one axis of magnetisation is twisted
G11C  11/14  \	2	2	5B002	G11C  11/14	6193	ǻҤѤ	using thin-film elements
G11C  11/15  \	3	3	5B073	G11C  11/15	39	¿ؤμؤѤΡʣǣãͥˡΣ	using multiple magnetic layers (G11C 11/155 takes precedence) [2]
G11C  11/155  \	3	3	5B073	G11C  11/155	591	ηͭΡΣ	with cylindrical configuration [2]
G11C  11/16  \	2	2	5B073	G11C  11/16	218	ѤŪԥ̤˴ŤƤǻҤѤ	using elements in which the storage effect is based on magnetic spin effect
G11C  11/16 100 \	3	3	5B073	G11C  11/16	11	ꥻ빽¤˴ؤ	related to memory cell structure
G11C  11/16 100 A	3	0	5B073	G11C  11/16	489	칽¤˴ؤ	related to thin film structure
G11C  11/16 100 C	3	0	5B073	G11C  11/16	370	ɰưȼ	with the movement of magnetic wall
G11C  11/16 100 Z	3	0	5B073	G11C  11/16	1138	¾	Others
G11C  11/16 200 \	3	3	5B073	G11C  11/16	238	ղϩ	Auxiliary circuits
G11C  11/16 210 \	4	4	5B073	G11C  11/16	28	ɥ쥹ϩޤϥɥ쥹ǥ	Address circuits or address decoders
G11C  11/16 212 \	5	5	5B073	G11C  11/16	184	ӥåޤϥϩ	Bit lines or column circuits
G11C  11/16 214 \	5	5	5B073	G11C  11/16	249	ޤϥϩ	Word lines or row circuits
G11C  11/16 220 \	4	4	5B073	G11C  11/16	138		Cell selection
G11C  11/16 230 \	4	4	5B073	G11C  11/16	1161	ɤ߽Ф󥷥󥰤βϩޤˡ	Reading or sensing circuits or methods
G11C  11/16 240 \	4	4	5B073	G11C  11/16	1456	񤭹ߡץߥ󥰤βϩޤˡ	Writing or programming circuits or methods
G11C  11/16 250 \	4	4	5B073	G11C  11/16	75	٥եϩޤˡ	Verifying circuits or methods
G11C  11/16 260 \	4	4	5B073	G11C  11/16	134	ߥ󥰲ϩޤˡ	Timing circuits or methods
G11C  11/16 280 \	4	4	5B073	G11C  11/16	33	ݸϩޤˡ	Protection circuits or methods
G11C  11/16 290 \	4	4	5B073	G11C  11/16	85	϶ϩ	Electric power supply circuits
G11C  11/18  \	1	1	5B067	G11C  11/18	48	ۡǻҤѤ	using Hall-effect devices
G11C  11/19  \	1	1	5B067	G11C  11/19	4	ϩˤͶƳǻҤѤΡΣ	using non-linear reactive devices in resonant circuits [2]
G11C  11/20  \	2	2	5B067	G11C  11/20	8	ѥȥѤΡΣ	using parametrons [2]
G11C  11/21  \	1	1	5B067	G11C  11/21	54	ŵŪǻҤѤΡΣ	using electric elements [2]
G11C  11/22  \	2	2	5B067	G11C  11/22	103	ͶǻҤѤΡΣ	using ferroelectric elements [2]
G11C  11/22 110 \	3	3	5B067	G11C  11/22	661	ͶΥѥѤ	using ferroelectric capacitors
G11C  11/22 120 \	3	3	5B067	G11C  11/22	221	ͶΥͭͣϣӤѤ	using MOS with ferroelectric gate insulating film
G11C  11/22 200 \	3	3	5B067	G11C  11/22	450	ղϩ	Auxiliary circuits
G11C  11/22 210 \	4	4	5B067	G11C  11/22	10	ɥ쥹ϩޤϥɥ쥹ǥ	Address circuits or address decoders
G11C  11/22 212 \	5	5	5B067	G11C  11/22	277	ӥåޤϥϩ	Bit lines or column circuits
G11C  11/22 214 \	6	6	5B067	G11C  11/22	135	ץ㡼ǥ㡼饤ϩ	Precharge, discharge, equalizing circuits
G11C  11/22 216 \	5	5	5B067	G11C  11/22	146	ޤϥϩ	Word lines or row circuits
G11C  11/22 218 \	5	5	5B067	G11C  11/22	314	ץ졼ϩ	Plate line circuits
G11C  11/22 220 \	4	4	5B067	G11C  11/22	40		Cell selection
G11C  11/22 230 \	4	4	5B067	G11C  11/22	255	ɤ߽Ф󥷥󥰤βϩޤˡ	Reading or sensing circuits or methods
G11C  11/22 232 \	5	5	5B067	G11C  11/22	215	󥹥	Sense amplifier
G11C  11/22 234 \	5	5	5B067	G11C  11/22	282	Űȯϩ㡥ߡ	Reference voltage generating circuits, e.g. dummy cells
G11C  11/22 240 \	4	4	5B067	G11C  11/22	247	񤭹ߡץߥ󥰤βϩޤˡ	Writing or programming circuits or methods
G11C  11/22 250 \	4	4	5B067	G11C  11/22	9	٥եϩޤˡ	Verifying circuits or methods
G11C  11/22 260 \	4	4	5B067	G11C  11/22	84	ߥ󥰲ϩޤˡ	Timing circuits or methods
G11C  11/22 270 \	4	4	5B067	G11C  11/22	49	ݻϡפɾ	Evaluation of degradation, retention or wearout
G11C  11/22 280 \	4	4	5B067	G11C  11/22	20	ݸϩޤˡ	Protection circuits or methods
G11C  11/22 290 \	4	4	5B067	G11C  11/22	37	϶ϩ	Electric power supply circuits
G11C  11/23  \	2	2	5B067	G11C  11/23	30	ĤζؾŵѤΡ㡥ե쥹ϥմɡʣǣãͥˡΣ	using electrostatic storage on a common layer, e.g. Forrester-Haeff tubes (G11C11/22 takes precedence) [2]
G11C  11/24  \	2	2	5B067	G11C  11/24	58	ѥѤΡʣǣãͥ表ȾƳ֤ȥѥȹ礻ѤΣǣã㡥ǣãˡΣ	using capacitors (G11C11/22 takes precedence; using a combination of a semiconductor device and a capacitor G11C11/34, e.g. G11C11/40) [2, 5]
G11C  11/26  \	2	2	5B067	G11C  11/26	4	ŴɤѤΡΣ	using discharge tubes [2]
G11C  11/28  \	3	3	5B067	G11C  11/28	14	ɤѤΡΣ	using gas-filled tubes [2]
G11C  11/30  \	3	3	5B067	G11C  11/30	63	ɤѤΡʣǣãͥˡΣ	using vacuum tubes (G11C11/23 takes precedence) [2]
G11C  11/34  \	2	2	5B015	G11C  11/34	13519	ȾƳ֤ѤΡΣ	using semiconductor devices [2]
G11C  11/35  \	3	3	5B015	G11C  11/35	0	ؤѤ줿Ų٤Ρ㡥Ųٷ֡Σ	with charge storage in a depletion layer, e.g. charge coupled devices [7]
G11C  11/36  \	3	3	5B015	G11C  11/36	38	ɤѤΡ㡥ǻҤȤѤΡΣ	using diodes, e.g. as threshold elements [2]
G11C  11/38  \	4	4	5B015	G11C  11/38	102	ȥͥɤѤΡΣ	using tunnel diodes [2]
G11C  11/39  \	3	3	5B015	G11C  11/39	68	ꥹѤΡΣ	using thyristors [5]
G11C  11/40  \	3	3	5B015	G11C  11/40	4	ȥ󥸥ѤΡΣ	using transistors [2]
G11C  11/401  \	4	4	5M024	G11C  11/401	6709	եå󥰤ޤŲٺʤʥߥåΣ	forming cells needing refreshing or charge regeneration, i.e. dynamic cells [5]
G11C  11/402  \	5	5	5M024	G11C  11/402	170	ơΥꥻ˸̤ŲٺʤեåĤΡΣ	with charge regeneration individual to each memory cell, i.e. internal refresh [5]
G11C  11/403  \	5	5	5M024	G11C  11/403	572	¿Υꥻ˶̤ŲٺʤեåĤΡΣ	with charge regeneration common to a multiplicity of memory cells, i.e. external refresh [5]
G11C  11/404  \	6	6	5M024	G11C  11/404	437	ĤΥꡤĤŲžȡ㡥ͣϣӥȥ󥸥ĤΡΣ	with one charge-transfer gate, e.g. MOS transistor, per cell [5]
G11C  11/404 100 \	7	7	5M024	G11C  11/404	187	줾줬̤ͭ롤ľ³줿ʣΥȥ󥸥	using a plurality of serially connected access transistors, each having a storage capacitor
G11C  11/405  \	6	6	5M024	G11C  11/405	1492	ĤΥꡤĤŲžȡ㡥ͣϣӥȥ󥸥ĤΡΣ	with three charge-transfer gates, e.g. MOS transistors, per cell [5]
G11C  11/406  \	5	5	5M024	G11C  11/406	389	եå󥰤ޤŲٺδޤΣ	Management or control of the refreshing or charge-regeneration cycles [5]
G11C  11/406 100 \	6	6	5M024	G11C  11/406	718	ɤ߽񤭤ޤϥեåưΤΥꥻۡͥ١Ʊ	Arbitration, priority and concurrent access to memory cells for read/write or refresh operation
G11C  11/406 102 \	7	7	5M024	G11C  11/406	116	ͥ٤˴Ťƥեå夹	refreshing based on priority
G11C  11/406 104 \	7	7	5M024	G11C  11/406	143	ɤ߽ưޤϥեåưǤ	interrupting read/write or refresh operation
G11C  11/406 110 \	7	7	5M024	G11C  11/406	118	󥢥˥եå夹	refreshing at no access
G11C  11/406 120 \	6	6	5M024	G11C  11/406	600	եåѲ	with changeable refresh cycles
G11C  11/406 140 \	6	6	5M024	G11C  11/406	508	եåεưޤϥեå奿ߥ󥰤ȯ˴ؤ	related to the activation of refresh or the generation of refresh timing
G11C  11/406 200 \	6	6	5M024	G11C  11/406	0	åޤϥǡХåեͭ뵭֤ˤեåư	Refresh operations in memory devices with an internal cache or data buffer
G11C  11/406 300 \	6	6	5M024	G11C  11/406	532	ޤʬŪեåưγߥ󥰡㡥ȥեåޤϣãӥӥեңӷեå	External triggering or timing of internal or partially internal refresh operation, e.g. auto-refresh or CAS-before-RAS triggered refresh
G11C  11/406 350 \	6	6	5M024	G11C  11/406	1181	եåޤϥߥ󥰡㡥ҥɥեå塤եեå塤ӣң	Internal triggering or timing for refresh, e.g., hidden refresh, self refresh, and pseudo-SRAM
G11C  11/406 400 \	6	6	5M024	G11C  11/406	813	ʣΥХ󥯤ޤϥ󥿡꡼֤ˤޤեåư	Refresh operation over multiple banks or interleaving
G11C  11/406 450 \	6	6	5M024	G11C  11/406	446	ꥢ쥤ʬեå	Partial refresh of memory arrays
G11C  11/406 460 \	6	6	5M024	G11C  11/406	367	եåάΤޤϥեå奢ɥ쥹ȯ˴ؤ	skipping refresh or related to the generation of refresh addresses
G11C  11/406 500 \	6	6	5M024	G11C  11/406	260	եåưȯǮ˴ؤ	Temperature related aspects of refresh operations
G11C  11/4063  \	5	5	5M024	G11C  11/4063	2912	ղϩ㡥ɥ쥹ѡǥѡưѡѡѡޤϥߥѡΣ	Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing [7]
G11C  11/4067  \	6	6	5M024	G11C  11/4067	0	Хݡ鷿ΥꡦѤμղϩΣ	Auxiliary circuits for memory cells of the bipolar type [7]
G11C  11/407  \	6	6	5M024	G11C  11/407	960	ų̷ΥꡦѤμղϩΣ	Auxiliary circuits for memory cells of the field-effect type [5]
G11C  11/4072  \	7	7	5M024	G11C  11/4072	637	ѥåפޤϥѥ󡤥ꥯꥢޤϥץꥻåѤβϩΣ	Circuits for initialization, powering up or down, clearing memory or presetting [7]
G11C  11/4074  \	7	7	5M024	G11C  11/4074	3537	϶ϩޤŰȯϩ㡥ХŰȯŰȯХååŸŸϩΣ	Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits [7]
G11C  11/4074 100 \	8	8	5M024	G11C  11/4074	68	Ÿ۾ޤϥƥк	Power abnormality or system down countermeasures
G11C  11/4074 150 \	8	8	5M024	G11C  11/4074	212	ХåƥꤪӥХååŸ	Battery and back-up supplies
G11C  11/4074 200 \	8	8	5M024	G11C  11/4074	323	ץ졼Ű	Plate voltage control
G11C  11/4074 250 \	8	8	5M024	G11C  11/4074	775	Ű	Substrate voltage control
G11C  11/4076  \	7	7	5M024	G11C  11/4076	2656	ߥ󥰲ϩʺѣǣãˡΣ	Timing circuits (for regeneration management G11C11/406) [7]
G11C  11/4078  \	7	7	5M024	G11C  11/4078	0	ޤݸϩ㡥դʡ뤤ɽФߤɤΤΡơ롨ƥȡʥåޤϥƥȤˤƤݸǣãˡΣ	Safety or protection circuits, e.g. for preventing inadvertent or unauthorized reading or writing; Status cells; test cells (protection of memory contents during checking or testing G11C29/52) [7]
G11C  11/408  \	7	7	5M024	G11C  11/408	4	ɥ쥹ϩΣ	Address circuits [5]
G11C  11/408 100 \	8	8	5M024	G11C  11/408	339	ɥ쥹Хåե٥Ѵϩ	Address buffers; Level converting circuits
G11C  11/408 120 \	8	8	5M024	G11C  11/408	2079	ϩ㡥ѤΥɥ饤С֡ץ륢åײϩץϩץ㡼ϩ	Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
G11C  11/408 125 \	9	9	5M024	G11C  11/408	172	ײϩ	Word line clamp circuits
G11C  11/408 140 \	8	8	5M024	G11C  11/408	1060	ɥ쥹ǥ㡥ӥåޤϥǥ¿ǥ	Address decoders, e.g. bit - or word line decoders; Multiple line decoders
G11C  11/409  \	7	7	5M024	G11C  11/409	17	ɽФݽߡΣҡݣסϲϩΣ	Read-write [R-W] circuits [5]
G11C  11/4091  \	8	8	5M024	G11C  11/4091	69	󥹤ޤϥ󥹡եåޤϥ󥹴Ϣϩ㡥ӥåФΥץ㡼饤ޤʬΥΣ	Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalizing or isolating [7]
G11C  11/4091 120 \	9	9	5M024	G11C  11/4091	732	βϩΤħΤ	characterised by circuits per se of a sense amplifier
G11C  11/4091 122 \	10	10	5M024	G11C  11/4091	627	ȥ󥹥եȤħΤΡ㡥ȥ󥹥եȤζưŰߥ󥰡Ųž̤Ѥ	characterised by transfer gates, e.g. using driving voltage, timing, and charge transfer effect of a transfer gate
G11C  11/4091 124 \	10	10	5M024	G11C  11/4091	214	ꥻξꥹȥ뤿βϩ㡤ƥ֥ꥹȥϩ	Circuits for restoring the information of a memory cell, e.g. active restore circuits
G11C  11/4091 140 \	9	9	5M024	G11C  11/4091	1472	ħΤ	characterised by control of sense amplifiers
G11C  11/4091 150 \	9	9	5M024	G11C  11/4091	340	ħΤ	characterised by sense methods
G11C  11/4091 160 \	9	9	5M024	G11C  11/4091	1566	ӥåΥץ㡼ħΤ	characterised by bit line precharge
G11C  11/4093  \	8	8	5M024	G11C  11/4093	972	ϡΣɡϡϥǡ󥿡ե㡥ǡХåեΣ	Input/output [I/O] data interface arrangements, e.g. data buffers [2006.01]
G11C  11/4093 100 \	9	9	5M024	G11C  11/4093	705	ϥǡХåեͭ	having input data buffers
G11C  11/4093 150 \	9	9	5M024	G11C  11/4093	1643	ϥǡХåեͭ	having output data buffers
G11C  11/4094  \	8	8	5M024	G11C  11/4094	14	ӥåޤϩΣ	Bit-line management or control circuits [7]
G11C  11/4096  \	8	8	5M024	G11C  11/4096	10	ϡΣɡϡϥǡޤϩ㡥ɽФޤϽ߲ϩɡϥɥ饤СӥååΣ	Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches [7]
G11C  11/4096 100 \	9	9	5M024	G11C  11/4096	1566	ϥХ	Input/output bus
G11C  11/4096 200 \	9	9	5M024	G11C  11/4096	481	ǡ	Data amplifiers
G11C  11/4096 300 \	9	9	5M024	G11C  11/4096	1558	⡼ɤޤϥ˴ؤ	related to access modes or access methods
G11C  11/4096 310 \	10	10	5M024	G11C  11/4096	356	ڡ⡼ɤ˴ؤ	related to page modes
G11C  11/4096 320 \	10	10	5M024	G11C  11/4096	115	˥֥⡼ɤ˴ؤ	related to nibble modes
G11C  11/4096 330 \	10	10	5M024	G11C  11/4096	109	Ū⡼ɤ˴ؤ	related to static column modes
G11C  11/4096 400 \	9	9	5M024	G11C  11/4096	911	ǥ奢ݡȥ˴ؤ	related to dual port memories
G11C  11/4096 450 \	9	9	5M024	G11C  11/4096	2392	Τʣʬޤϥ֥åʬ䤵줿륢쥤˴ؤΡʣǣãͥ	Related to the whole of a cell array that is divided into a plurality of sections or blocks (G11C11/406, 400 takes precedence)
G11C  11/4096 500 \	9	9	5M024	G11C  11/4096	2328	󥯥ʥ	Synchronous memory
G11C  11/4096 550 \	10	10	5M024	G11C  11/4096	866	ģģ	DDR
G11C  11/4097  \	8	8	5M024	G11C  11/4097	1131	ӥå㡥ӥå쥤ȡ֤ӥåΣ	Bit-line organization, e.g. bit-line layout, folded bit lines [7]
G11C  11/4099  \	8	8	5M024	G11C  11/4099	809	ߡեŰȯΣ	Dummy cell treatment; Reference voltage generators [7]
G11C  11/41  \	4	4	5B015	G11C  11/41	923	Ԥˤ륻롤ʤեå󥰤ޤŲٺɬפȤʤΡ㡥аޥХ֥졼ޤϥߥåȥȥꥬΣ	forming cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger [5]
G11C  11/411  \	5	5	5B015	G11C  11/411	636	Хݡȥ󥸥ΤߤѤΡΣ	using bipolar transistors only [5]
G11C  11/412  \	5	5	5B015	G11C  11/412	2235	ų̥ȥ󥸥ΤߤѤΡΣ	using field-effect transistors only [5]
G11C  11/412 100 \	6	6	5B015	G11C  11/412	296	ӼФݸΤβϩʤ줿ʰ̣ǣã	Cells incorporating circuit means for protection against loss of information (in general G11C5/00, 100)
G11C  11/412 110 \	6	6	5B015	G11C  11/412	155	ŪȤʿե˴ؤ	related to unbalanced cells for initialization purpose
G11C  11/412 120 \	6	6	5B015	G11C  11/412	268	ǡɽФޤϽޤ	designed to read or write data from one of a pair of cells
G11C  11/413  \	5	5	5B015	G11C  11/413	14	ղϩ㡥ɥ쥷󥰡沽ưߡΡƱϲѡΣ	Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, synchronizing or power reduction [5]
G11C  11/414  \	6	6	5B015	G11C  11/414	84	Хݡ鷿ΥꥻѡΣ	for memory cells of the bipolar type [5]
G11C  11/415  \	7	7	5B015	G11C  11/415	152	ɥ쥹ϩΣ	Address circuits [5]
G11C  11/416  \	7	7	5B015	G11C  11/416	912	ɽФݽ߲ϩΣҡݣסϡΣ	Read-write [R-W] circuits [5]
G11C  11/417  \	6	6	5B015	G11C  11/417	8	ų̷ΥꥻѡΣ	for memory cells of the field-effect type [5]
G11C  11/417 100 \	7	7	5B015	G11C  11/417	1211	Ÿϩ	Power supply circuits
G11C  11/417 110 \	8	8	5B015	G11C  11/417	291	ХåƥХååפ˴ؤ	related to battery backup
G11C  11/417 120 \	8	8	5B015	G11C  11/417	256	ĥХ˴ؤ	related to substrate bias
G11C  11/418  \	7	7	5B015	G11C  11/418	1	ɥ쥹ϩΣ	Address circuits [5]
G11C  11/418 100 \	8	8	5B015	G11C  11/418	9	ɥ쥹ϩ	Address selection circuits
G11C  11/418 110 \	9	9	5B015	G11C  11/418	1040	ޤ϶ư˴ؤ	related to selection or drive
G11C  11/418 120 \	9	9	5B015	G11C  11/418	869	ʬ䡤ɥ쥹ʬ˴ؤ	related to memory division and address division
G11C  11/418 130 \	9	9	5B015	G11C  11/418	884	ɥ쥹ǥϩ	Address decoder circuits
G11C  11/418 140 \	9	9	5B015	G11C  11/418	267	ɥ쥹Хåեϩ	Address buffer circuits
G11C  11/419  \	7	7	5B015	G11C  11/419	60	ɽФݽ߲ϩΣҡݣסϡΣ	Read-write [R-W] circuits [5]
G11C  11/419 100 \	8	8	5B015	G11C  11/419	1519	ϩ	Sense amplification circuits
G11C  11/419 110 \	8	8	5B015	G11C  11/419	566	ɥ쥹ѲΤƽư㡥ץ㡼Ԥ	performing intended operation, e.g. precharge, by detecting changes in addresses
G11C  11/419 120 \	8	8	5B015	G11C  11/419	794	ץ㡼˴ؤΡʣǣãͥ	related to precharge (G11C 11/419, 110 takes precedence)
G11C  11/419 130 \	8	8	5B015	G11C  11/419	1172	ϡΣɡϡϥǡ󥿡ե	Input/output [I/O] data interface arrangements
G11C  11/419 140 \	8	8	5B015	G11C  11/419	971	󥯥ʥ	Synchronous memory
G11C  11/4193  \	3	3	5B015	G11C  11/4193	1	üȾƳε֤ͭμ֡㡥ɥ쥷󥰡ưСߥ󥰡϶롤ãΤΤΡʣǣãǣãͥˡΣ	Auxiliary circuits specific to particular types of semiconductor storage devices, e.g. for addressing, driving, sensing, timing, power supply, signal propagation (G11C11/4063, G11C11/413 take precedence) [7]
G11C  11/4195  \	4	4	5B015	G11C  11/4195	0	ɥ쥹ϩΣ	Address circuits [7]
G11C  11/4197  \	4	4	5B015	G11C  11/4197	1	ɽФݽ߲ϩΣҡݣסϡΣ	Read-write [R-W] circuits [7]
G11C  11/42  \	2	2	5B067	G11C  11/42	507	ץȡݥ쥯ȥ˥֡ʤŵŪޤϸŪ˷礵줿ͤӸŵ֤Ѥ	using opto-electronic devices, i.e. light-emitting and photoelectric devices electrically- or optically-coupled
G11C  11/44  \	2	2	5B067	G11C  11/44	400	ĶƳǻҡ㡥饤ȥ󡤤ѤΡΣ	using super-conductive elements, e.g. cryotron [2]
G11C  11/46  \	1	1	5B067	G11C  11/46	18	ǮǻҤѤ	using thermoplastic elements
G11C  11/48  \	1	1	5B067	G11C  11/48	1	ߤޤϼʥ󥹤ۤʤ֤δ֤Ѳ뤿ΰưǽʷǻҡ㡥Ѥ	using displaceable coupling elements, e.g. ferromagnetic cores, to produce change between different states of mutual or self-inductance
G11C  11/50  \	1	1	5B067	G11C  11/50	26	򵭲뤿ŵưΡΣ	using actuation of electric contacts to store the information [2006.01]
G11C  11/52  \	2	2	5B067	G11C  11/52	9	ż졼Ѥ	using electromagnetic relays
G11C  11/54  \	1	1	5B067	G11C  11/54	530	ʪ˦㡥˥塼󡤤򥷥ߥ졼󤷤ǻҤѤ	using elements simulating biological cells, e.g. neuron
G11C  11/56  \	1	1	5B067	G11C  11/56	24	ƥåפˤäɽ蘆룲ĤޤϤʾοΰ֤ĵǻҤѤΡ㡥ŰˤΡήˤΡˤΡȿˤΡΣ	using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency [2006.01]
G11C  11/56 100 \	2	2	5B073	G11C  11/56	193	ǻҤѤ	using magnetic storage elements
G11C  11/56 150 \	2	2	5B067	G11C  11/56	32	Ƴ֥åңͤޤϥץǽʶ°ʪѤ	using conductive bridging RAM [CBRAM] or programmable metallization cells [PMC]
G11C  11/56 200 \	2	2	5B225	G11C  11/56	2097	ͷȤˤŲѤѤ	using charge storage in a floating gate
G11C  11/56 210 \	3	3	5B225	G11C  11/56	1407	ץߥ󥰤ޤϽ߲ϩǡϲϩ	Programming or writing circuits; Data input circuits
G11C  11/56 215 \	4	4	5B225	G11C  11/56	210	õϩ	Erasing circuits
G11C  11/56 220 \	3	3	5B225	G11C  11/56	924	ΤޤɽФϩǡϲϩ	Detecting or reading circuits; Data output circuits
G11C  11/56 250 \	2	2	5M024	G11C  11/56	409	ŲǻҤѤ	using capacitive charge storage elements
G11C  11/56 300 \	2	2	5B067	G11C  11/56	84	ͶεǻҤѤ	using ferroelectric storage elements
G11C  11/56 350 \	2	2	5B067	G11C  11/56	5	ͭǻҤѤ	using organic material storage elements
G11C  11/56 400 \	2	2	5B225	G11C  11/56	353	ΤˤŲ٥ȥåԥ󥰤Ѥ	using charge trapping in an insulator
G11C  11/56 450 \	2	2	5B067	G11C  11/56	146	ե뾽ѲǻҤѤ	using amorphous/crystalline phase transition storage elements
G11C  11/56 500 \	2	2	5B067	G11C  11/56	117	°ʪǻҡ㡥ڥ֥ȤѤ	using storage elements comprising metal oxide memory material, e.g. perovskites
G11C  11/56 600 \	2	2	5B225	G11C  11/56	134	ޥӥåɽФѥ	Multi-bit read-only memory
G11C  13/00  \	0	0	5B067	G11C  13/00	48	ǣãǣãޤϣǣãޤʤǻҤλѤˤäħŤ줿ǥ뵭	Digital stores characterised by the use of storage elements not covered by groups G11C 11/00, G11C 23/00, or G11C 25/00
G11C  13/00 200 \	1	1	5B067	G11C  13/00	117	񹳥ॢǻҤѤ	using resistance random access memory element
G11C  13/00 210 \	2	2	5B067	G11C  13/00	977	ե뾽ѲǻҤޤ	including amorphous/memory element of chrystal
G11C  13/00 215 \	2	2	5B067	G11C  13/00	1159	°ʪǻҤޤ	including metallic oxide memory element
G11C  13/00 220 \	2	2	5B067	G11C  13/00	28	°ⲽʪǻҤޤ	including metallic nitride memory element
G11C  13/00 225 \	2	2	5B067	G11C  13/00	6	Ѳ˰¸뵭ǻҤޤ	including storaage element depending onchemical change
G11C  13/00 230 \	3	3	5B067	G11C  13/00	340	Ƴ֥åǻҤޤϥץǽʶ°ʪǻҤޤ	including conductive bridge storage element or programmable metallic compound storage element
G11C  13/00 235 \	3	3	5B067	G11C  13/00	4	ͭǻҤޤ	including organic materials atorage element
G11C  13/00 235 A	3	0	5B067	G11C  13/00	68	ݥޡޤ	including polymer
G11C  13/00 235 B	3	0	5B067	G11C  13/00	5	ХʬҤޤ	including
G11C  13/00 235 Z	3	0	5B067	G11C  13/00	1	¾Τ	Others
G11C  13/00 240 \	2	2	5B067	G11C  13/00	35	ʥΥ塼ֵǻҤޤ	including nano tube storage element
G11C  13/00 245 \	2	2	5B067	G11C  13/00	17	ʥΥå׵ǻҤޤ	including nano gap storage element
G11C  13/00 270 \	2	2	5B067	G11C  13/00	0	륢쥤η֤ħ	characterized by shape of cell array
G11C  13/00 270 A	2	0	5B067	G11C  13/00	353	쥤	3 dimensional array
G11C  13/00 270 B	2	0	5B067	G11C  13/00	488	ǻҤɤǤ륢쥤	array with selective element being diode
G11C  13/00 270 C	2	0	5B067	G11C  13/00	32	ǻҤεǽȰβǻҵǽ㡥ɵǽĥ쥤	function of selective element integrated with strage function of storage element, e.g. array having function of diode
G11C  13/00 270 D	2	0	5B067	G11C  13/00	34	İʾǻҤƵ뤬ĥ쥤	aray with each storage sell having two or more selective element
G11C  13/00 270 E	2	0	5B067	G11C  13/00	87	ȥ󥸥³줿ǻҤľ³줿󡤤ʤΣΣĹ¤ĥ쥤	array having a row of storage elements forming storage elements connected to selective transistor in parallel are connected in series, i.e. NAND structure
G11C  13/00 270 F	2	0	5B067	G11C  13/00	128	ȥ󥸥ǤɤǤʤǻҤƥΤ˻Ѥ륢쥤	array using non-transistor and non-diode selective elements for each cell
G11C  13/00 270 G	2	0	5B067	G11C  13/00	265	ǻҤѤ뤳ȤʤӥåȥľŪ³줿ǻҤĥ쥤	array having storage element directly connected to bit line and word line without using selective element
G11C  13/00 270 H	2	0	5B067	G11C  13/00	79	췲ε뤬ǻҤͭ륢쥤	array with a group of storage sells jointly owning selective element
G11C  13/00 270 J	2	0	5B067	G11C  13/00	411	ǻҤȥ󥸥Ǥ륢쥤	array with selective element being transistor
G11C  13/00 270 K	2	0	5B067	G11C  13/00	1	ġ롤ǻҤͭǷ줿쥤	array with substrate, cell, wiring and selective element are all formed by organic materials
G11C  13/00 270 Z	2	0	5B067	G11C  13/00	79	¾ħ륢쥤	array having other characteristics
G11C  13/00 300 \	2	2	5B067	G11C  13/00	69	ղϩ	peripheral circuit
G11C  13/00 310 \	3	3	5B067	G11C  13/00	10	ɥ쥹ϩޤϥɥ쥹ǥ	address circuit or address decoder
G11C  13/00 312 \	4	4	5B067	G11C  13/00	118	ӥåޤϥϩ	bit line or column circuit
G11C  13/00 314 \	4	4	5B067	G11C  13/00	79	ޤϥϩ	word line or row circuit
G11C  13/00 320 \	3	3	5B067	G11C  13/00	54		cell selection
G11C  13/00 340 \	3	3	5B067	G11C  13/00	146	ǥ֤ɻߡǥ֤ɾǥ֤줿ǡΥեå	prevention of distgurb, evaluation of disturb; refreshing disturbed storage data
G11C  13/00 360 \	3	3	5B067	G11C  13/00	178	ݻϡפɾ	evaluation of deterioration, holding power, exhaustion
G11C  13/00 380 \	3	3	5B067	G11C  13/00	54	϶ϩ	electric power supplying circuit
G11C  13/00 400 \	3	3	5B067	G11C  13/00	7	ɤ߽Ф󥷥󥰤βϩޤˡ	circuit or method of read out, sensing
G11C  13/00 400 A	3	0	5B067	G11C  13/00	15	ʬΡ㡥ӥåˤɤ߽Ф	difference detection, e.g. read out by complementary bit line
G11C  13/00 400 B	3	0	5B067	G11C  13/00	471	ήˤɤ߽Ф	read out by cell current
G11C  13/00 400 C	3	0	5B067	G11C  13/00	28	˲ɤ߽Ф	destructive read out
G11C  13/00 400 D	3	0	5B067	G11C  13/00	136	Ŷ˴֤Ű̺ˤɤ߽Ф	read out by potential difference between cell electrodes
G11C  13/00 400 E	3	0	5B067	G11C  13/00	200	ӥåץ㡼ɤ߽Ф	read out after bit line precharge
G11C  13/00 400 F	3	0	5B067	G11C  13/00	74	ɤ߽Фѥ륹η㡥⤵ˤäħդ줿ɤ߽Ф	shape of read out pulse, e.g. read out characterized by shape, width, height
G11C  13/00 400 G	3	0	5B067	G11C  13/00	161	ե󥹥ȤӤˤäƼ¹Ԥɤ߽Ф	read out executed by comparison with reference cell
G11C  13/00 400 H	3	0	5B067	G11C  13/00	30	ʥեˤäƼ¹Ԥɤ߽Ф	read out executed by self reference system
G11C  13/00 400 Z	3	0	5B067	G11C  13/00	10	¾ɤ߽Ф	other readout
G11C  13/00 420 \	3	3	5B067	G11C  13/00	55	ƥݸϩޤˡ	circuit or method for security, protection
G11C  13/00 440 \	3	3	5B067	G11C  13/00	82	ߥ󥰲ϩޤˡ	circuit or method for timing
G11C  13/00 460 \	3	3	5B067	G11C  13/00	0	٥եϩޤˡ	circuit or method for verifying
G11C  13/00 462 \	4	4	5B067	G11C  13/00	82	񤭹񤭹ޤ줿Ȥ٥ե	to verify entry was made correctly during writing
G11C  13/00 464 \	4	4	5B067	G11C  13/00	301	񤭹߸񤭹ޤ줿Ȥ٥ե	to verify entry was made correctly after writing
G11C  13/00 480 \	3	3	5B067	G11C  13/00	8	񤭹ߡץߥ󥰤βϩޤˡ	circuit or method for writing, programming
G11C  13/00 480 A	3	0	5B067	G11C  13/00	72	ǻҤΥȤ˽񤭹Ṳ̋ä񤭹	writing to apply electrical potential of writing to gate of selective element
G11C  13/00 480 B	3	0	5B067	G11C  13/00	680	ξ˥Űä񤭹	writing to apply cell voltage to two directions
G11C  13/00 480 C	3	0	5B067	G11C  13/00	110	ɤ߽Ф̤˴ŤƼ¹Ԥ񤭹	execute writing based on result of read out
G11C  13/00 480 D	3	0	5B067	G11C  13/00	153	ήή̤ˤ񤭹	writing by amperage of flow through cell
G11C  13/00 480 E	3	0	5B067	G11C  13/00	59	μϤǮȯ뤳Ȥˤ񤭹	writing by generating heat around storage materials
G11C  13/00 480 F	3	0	5B067	G11C  13/00	213	եߥ󥰽Τν񤭹	writing for foaming treatment
G11C  13/00 480 G	3	0	5B067	G11C  13/00	110	ڡޤϣ㡥ʬʬƱ񤭹	1 page or 1 sector, e.g. simultaneous writing for 1 line, for 1 word line
G11C  13/00 480 H	3	0	5B067	G11C  13/00	209	ʣΥƱ񤭹	simultaneous writing in multiple cells
G11C  13/00 480 J	3	0	5B067	G11C  13/00	321	Ŷ˴֤Ű̺ä뤳Ȥˤ񤭹	writing by applying potential difference between cell electrodes
G11C  13/00 480 K	3	0	5B067	G11C  13/00	416	񤭹ߥѥ륹η㡥⤵ˤäħդ줿񤭹	shape of writing pulse, e.g. writing characterized by shape, width, height
G11C  13/00 480 L	3	0	5B067	G11C  13/00	7	Ǯ̤ˤĤߡ㡤ԥ쥯ȥåѤ񤭹	distoration by heat effect, e.g. writing using piezoelectric
G11C  13/00 480 Z	3	0	5B067	G11C  13/00	8	¾	Others
G11C  13/00 500 \	3	3	5B067	G11C  13/00	40	õ㡥ꥻåȤβϩޤˡ	deletion, e.g. circuit or method of resetting
G11C  13/02  \	1	1	5B067	G11C  13/02	52	ѲˤäƺưǻҤѤΡΣ	using elements whose operation depends upon chemical change [2006.01]
G11C  13/02 100 \	2	2	5B067	G11C  13/02	16	ե顼ѤΡ㡥ܥʥΥ塼֤ޤϥꥳʥΥ塼	using fulleren, e.g. carbon nano tube or silicon nano tube
G11C  13/04  \	1	1	5B067	G11C  13/04	805	ŪǻҤѤ	using optical elements
G11C  13/04 100 \	2	2	5B067	G11C  13/04	25	ۥȥߥåǻҤѤ	using photochromic storage element
G11C  13/04 200 \	2	2	5B067	G11C  13/04	0	ļʤηǵѤΡʥۥࡤåץޥ󡨥ۥեǣȡǣ£	using information stored in shape of interference fringes (hologram, Lipman; holography G03H, G02B5/32)
G11C  13/04 200 A	2	0	5B067	G11C  13/04	1	صǻҤѤ	using magneto-optics storage element
G11C  13/04 200 B	2	0	5B067	G11C  13/04	338	ŵصǻҤѤ	using electro-optics storage element
G11C  13/04 200 C	2	0	5B067	G11C  13/04	6	ۥȥߥåǻҤѤ	using photochromic storage element
G11C  13/04 200 Z	2	0	5B067	G11C  13/04	1	¾εǻҤѤ	using other storage element
G11C  13/04 300 \	2	2	5B067	G11C  13/04	18	ŵصǻҤѤ	using electro-optics storage element
G11C  13/04 400 \	2	2	5B067	G11C  13/04	12	¾εǻҤѤ	using other storage element
G11C  13/06  \	2	2	5B067	G11C  13/06	465	ݸǻҤѤΡΣ	using magneto-optical elements [2006.01]
G11C  14/00  \	0	0	5B094	G11C  14/00	1	Ÿǻ˥Хååפ뤿ΡȯꥻԴȯꥻ֤ˤäħŤ줿ǥ뵭֡Σ	Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down [5]
G11C  14/00 100 \	1	1	5B094	G11C  14/00	6	ȯǻҤģңͥǤ	in which the volatile element is a DRAM cell
G11C  14/00 110 \	2	2	5B094	G11C  14/00	77	ԴȯǻҤţţУңϣǻҡ㡥ͷȤޤϣͣΣϣӥȥ󥸥Ǥ	and the nonvolatile element is an EEPROM element, e.g. a floating gate or MNOS transistor
G11C  14/00 120 \	2	2	5B094	G11C  14/00	14	ԴȯǻҤͶǻҤǤ	and the nonvolatile element is a ferroelectric element
G11C  14/00 130 \	2	2	5B094	G11C  14/00	6	ԴȯǻҤңǻҡΣͣң͡Ϥޤ϶ǻҤǤ	and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic element
G11C  14/00 140 \	2	2	5B094	G11C  14/00	5	ԴȯǻҤѲңǻҤǤ	and the nonvolatile element is a resistive RAM element
G11C  14/00 200 \	1	1	5B094	G11C  14/00	157	ȯǻҤӣңͥǤ	in which the volatile element is a SRAM cell
G11C  14/00 210 \	2	2	5B094	G11C  14/00	367	ԴȯǻҤţţУңϣǻҡ㡥ͷȤޤϣͣΣϣӥȥ󥸥Ǥ	and the nonvolatile element is an EEPROM element, e.g. a floating gate or MNOS transistor
G11C  14/00 220 \	2	2	5B094	G11C  14/00	110	ԴȯǻҤͶǻҤǤ	and the nonvolatile element is a ferroelectric element
G11C  14/00 230 \	2	2	5B094	G11C  14/00	143	ԴȯǻҤңǻҡΣͣң͡Ϥޤ϶ǻҤǤ	and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic element
G11C  14/00 240 \	2	2	5B094	G11C  14/00	52	ԴȯǻҤѲңǻҤǤ	and the nonvolatile element is a resistive RAM element
G11C  15/00  \	0	0	5B095	G11C  15/00	1	ĤޤϤʾħŪʬʤ󤬽񤭹ޤ졤ɽФϤΣĤޤϰʾħŪʬˤĤõ뤳ȤˤäƹԤʤǥ뵭֡ʤϢ۵ޤƥɥ쥹֡Σ	Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores [2006.01]
G11C  15/00  A	0	0	5B095	G11C  15/00	78	ŪǻҤѤ	Using optical elements
G11C  15/00  Z	0	0	5B095	G11C  15/00	123	¾ΤΡĶƳǻҤѤ	Others (such as using superconductive elements)
G11C  15/02  \	1	1	5B095	G11C  15/02	87	ŪǻҤѤΡΣ	using magnetic elements [2]
G11C  15/04  \	1	1	5B095	G11C  15/04	5	ȾƳǻҤѤΡΣ	using semiconductor elements [2]
G11C  15/04  C	1	0	5B095	G11C  15/04	146	®ǽΨ	With higher speed and efficiency
G11C  15/04  D	1	0	5B095	G11C  15/04	63	ϻѤ	Using addressable memory
G11C  15/04  E	1	0	5B095	G11C  15/04	62	ʪ	Saving hardware
G11C  15/04  F	1	0	5B095	G11C  15/04	103	ưк	Countermeasures against malfunctions
G11C  15/04  Z	1	0	5B095	G11C  15/04	232	¾	Others
G11C  15/04 601 \	2	2	5B095	G11C  15/04	3	ϩ	cell circuits
G11C  15/04 601 A	2	0	5B095	G11C  15/04	246	ȯǻ	Volatile elements
G11C  15/04 601 R	2	0	5B095	G11C  15/04	118	Դȯǻ	Nonvolatile elements
G11C  15/04 601 S	2	0	5B095	G11C  15/04	23	üǻ	Special elements
G11C  15/04 601 W	2	0	5B095	G11C  15/04	106	ӵǽħΤΡ羮ӵǽޥǽ򥻥ߤΡ	Characterised by comparison functions (having a size comparison function and mask function within the cell)
G11C  15/04 601 Z	2	0	5B095	G11C  15/04	24	¾Τ	Others
G11C  15/04 631 \	2	2	5B095	G11C  15/04	4	ղϩ	peripheral circuits
G11C  15/04 631 A	2	0	5B095	G11C  15/04	47		In general
G11C  15/04 631 B	2	0	5B095	G11C  15/04	72	ʣȤ߹碌	Combinations of a plurality of memory
G11C  15/04 631 C	2	1	5B095	G11C  15/04	72	ãͤȰ̤ΥȤ߹碌	Combinations of a CAM and general memory
G11C  15/04 631 D	2	1	5B095	G11C  15/04	81	ãͤȣãͤȤ߹碌	Combinations of one CAM with another CAM
G11C  15/04 631 E	2	0	5B095	G11C  15/04	110	ãͥꥢ쥤ʬ	Performing memory management by division within CAM memory array
G11C  15/04 631 F	2	0	5B095	G11C  15/04	296	ӲϩħΤ	Characterized by comparison circuits
G11C  15/04 631 G	2	0	5B095	G11C  15/04	88	ͥϩħΤ	Characterized by preferred circuits
G11C  15/04 631 M	2	0	5B095	G11C  15/04	65	ޥϩħΤ	Characterized by mask circuits
G11C  15/04 631 W	2	0	5B095	G11C  15/04	102	ϢˡΤħΤ	Characterized by associative methods per se
G11C  15/04 631 Z	2	0	5B095	G11C  15/04	234	¾Τ	Others
G11C  15/06  \	1	1	5B095	G11C  15/06	13	饤˥åǻҤѤΡΣ	using cryogenic elements [2]
G11C  16/00  \	0	0	5B225	G11C  16/00	0	õǽǥץǽʥ꡼ɥʣǣãͥˡΣ	Erasable programmable read-only memories(G11C14/00 takes precedence) [5]
G11C  16/02  \	1	1	5B225	G11C  16/02	2909	ŵŪ˥ץǽʤΡΣ	electrically programmable [5]
G11C  16/04  \	2	2	5B225	G11C  16/04	1076	ͤѤʥȥ󥸥ѤΡ㡥ƣͣϣӡΣ	using threshold-variable transistors, e.g. FAMOS [5]
G11C  16/04 100 \	3	3	5B225	G11C  16/04	6	եƥ󥰥ȥȥ󥸥ޤ륻ǹΡʣǣãǣãͥ	comprising cells containing floating gate transistors (G11C 16/04, 170, G11C 16/04, 180 take precedence)
G11C  16/04 110 \	4	4	5B225	G11C  16/04	387	ñΥեƥ󥰥ȥȥ󥸥ޤȥ󥸥ޤʤǹΡ㡥գ֡ţУңϣ	comprising cells containing a single floating gate transistor and no selection transistor, e.g. UV EPROM
G11C  16/04 120 \	4	4	5B225	G11C  16/04	567	ޡ줿եƥ󥰥Ȥȥ󥸥ޤ륻ǹ	comprising cells containing a merged floating gate and selection transistor
G11C  16/04 130 \	4	4	5B225	G11C  16/04	693	ĤΥեƥ󥰥ȥȥ󥸥ӣİʾ̸Ĥȥ󥸥ޤ륻ǹ	comprising cells containing a single floating gate transistor and one separate selection transistors or more
G11C  16/04 140 \	4	4	5B225	G11C  16/04	515	ʣΥեƥ󥰥ȥǥХǹ륻롤㡥ʣΥեƥ󥰥Ȥ³줿̸ĤɽФڤӽߣƣͣϣӥȥ󥸥ޤ륻ǹ	comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors connected to multiple floating gates
G11C  16/04 143 \	5	5	5B225	G11C  16/04	6	ХͥȣΥͥȥ󥸥եƥ󥰥ȥꥻ롤̾϶̥եƥ󥰥Ȥͭ	Floating gate memory cells with both P and N channel memory transistors, usually sharing a common floating gate
G11C  16/04 146 \	5	5	5B225	G11C  16/04	10	Ωǡ򵭲ʣΩեƥ󥰥ȤǹΡñΥեƥ󥰥Ȥˤƣİʾΰ֤򵭲뤿ΤΣǣã	comprising plural independent floating gates which store independent data (for storage of more than two stable states at a single floating gate G11C11/56)
G11C  16/04 150 \	3	3	5B225	G11C  16/04	729	ؤŲ٤Ѥ륻ǹΡ㡥ͣΣϣӡӣΣϣӡʣǣãǣãͥ	comprising cells accumulating charges in an insulation layer, e.g. MNOS, SNOS (G11C 16/04, 170, G11C 16/04, 180 take precedence)
G11C  16/04 160 \	4	4	5B225	G11C  16/04	269	ΩǡݻʣΩȤǹΡñεȤˣʾΰꤷ֤Ѥ륹ȥ졼ǣã	comprising plural independent storage sites which store independent data (for storage of two or more stable states at a single storage site G11C11/56)
G11C  16/04 170 \	3	3	5B225	G11C  16/04	3168	ľ³줿ʣεȥ󥸥ͭ륻ǹ	comprising cells having several storage transistors connected in series
G11C  16/04 180 \	3	3	5B225	G11C  16/04	624	ϥ쥤	Virtual ground arrays
G11C  16/06  \	2	2	5B225	G11C  16/06	2375	ղϩ㡥ؤνѡΣ	Auxiliary circuits, e.g. for writing into memory [2006.01]
G11C  16/08  \	3	3	5B225	G11C  16/08	117	ɥ쥹ϩǥϩΣ	Address circuits; Decoders; Word-line control circuits [7]
G11C  16/08 100 \	4	4	5B225	G11C  16/08	21	ǥ	Column decoders
G11C  16/08 110 \	4	4	5B225	G11C  16/08	521	򡨥ǥ	Word line selection; Decoders
G11C  16/08 120 \	5	5	5B225	G11C  16/08	884	ưϩä˥ؤɽФŰζ	Word line driving circuits; Specially for supplying reading voltage to word lines
G11C  16/08 123 \	5	5	5B225	G11C  16/08	227	ưϩä˥٥եɽФ	Word line driving circuits; Specially for verifying reading
G11C  16/08 130 \	5	5	5B225	G11C  16/08	760	ưϩä˥ؤνŰζ	Word line driving circuits; Specially for supplying writing voltage to word lines
G11C  16/08 140 \	5	5	5B225	G11C  16/08	363	ưϩä˥ؤξõŰζ	Word line driving circuits; Specially for supplying deletion voltage to word lines
G11C  16/10  \	3	3	5B225	G11C  16/10	952	ץߥ󥰤ޤϥǡϲϩΣ	Programming or data input circuits [7]
G11C  16/10 100 \	4	4	5B225	G11C  16/10	755	ץߥ󥰲ϩ㡥ţУңϣͥץޡ󥵡åȥץߥ󥰤ޤϺƥץߥ󥰡ţУңϣͥߥ졼	External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
G11C  16/10 103 \	5	5	5B225	G11C  16/10	63	ä˿ǤִݾڤǰǵǽͭԴȯƤ򹹿ϩ㡥ǡμ¤˽񤭹ޤޤǸŤǡӼɤ	Circuits or methods for updating contents of nonvolatile memory, specially with &apos;security&apos; features to ensure reliable replacement, e.g. preventing loss of old data before new data is reliably written
G11C  16/10 110 \	4	4	5B225	G11C  16/10	161	쥤ޤϥ֥åõƱ֤˥ץߥ󥰤	Programming all cells in an array, sector or block to the same state prior to deletion
G11C  16/10 120 \	4	4	5B225	G11C  16/10	111	ΥǡӤ	comparing data with the data prior to writing
G11C  16/10 130 \	4	4	5B225	G11C  16/10	111	ȿžߡɽߤԤ	performing reverse write/typical write
G11C  16/10 140 \	4	4	5B225	G11C  16/10	1412	߻֡Űή	controlling write time/write voltage/write currents
G11C  16/10 143 \	4	4	5B225	G11C  16/10	331	ħ	characterised by source line control
G11C  16/10 150 \	4	4	5B225	G11C  16/10	1058	ü⡼ɤˤץ	program in a special mode
G11C  16/10 160 \	4	4	5B225	G11C  16/10	413	ХåեѤ	writing with buffer memory
G11C  16/10 170 \	4	4	5B225	G11C  16/10	277	ǡϲϩ	Data input circuits
G11C  16/12  \	4	4	5B225	G11C  16/12	26	ץߥŰå󥰲ϩΣ	Programming voltage switching circuits [7]
G11C  16/14  \	4	4	5B225	G11C  16/14	626	ŵŪ˾õ뤿βϩ㡥õŰå󥰲ϩΣ	Circuits for erasing electrically, e.g. erase voltage switching circuits [7]
G11C  16/14 100 \	5	5	5B225	G11C  16/14	718	õ֡õŰ	Delete time/delete voltage control
G11C  16/14 110 \	5	5	5B225	G11C  16/14	272	ħ	characterised by source line control
G11C  16/16  \	5	5	5B225	G11C  16/16	605	֥åõѤΤΡ㡥쥤ʣɡ롼סΣ	for erasing blocks, e.g. arrays, words, groups [7]
G11C  16/18  \	4	4	5B225	G11C  16/18	328	Ū˾õ뤿βϩΣ	Circuits for erasing optically [7]
G11C  16/20  \	4	4	5B225	G11C  16/20	111	ǡΥץꥻåȡåפμ̡Σ	Initializing; Data preset; Chip identification [7]
G11C  16/22  \	3	3	5B225	G11C  16/22	1412	ꡦؤʡޤθΥɤΰޤݸϩΣ	Safety or protection circuits preventing unauthorized or accidental access to memory cells [7]
G11C  16/22 100 \	4	4	5B225	G11C  16/22	34	ŸŰϰϳΤȤ˾õץߥ󥰡ޤɼɻߤ	Preventing deletion, programming or reading when power supply voltages are outside the required ranges
G11C  16/24  \	3	3	5B225	G11C  16/24	319	ӥåϩΣ	Bit-line control circuits [7]
G11C  16/24 100 \	4	4	5B225	G11C  16/24	569	ӥå˴ؤ	related to the selection of bit lines
G11C  16/24 110 \	4	4	5B225	G11C  16/24	924	ץ㡼ǥ㡼ϩ	Precharge/discharge circuits
G11C  16/24 120 \	4	4	5B225	G11C  16/24	414	Űȯϩ	Write voltage generation circuits
G11C  16/24 130 \	4	4	5B225	G11C  16/24	760	åϩ	Latch circuits
G11C  16/26  \	3	3	5B225	G11C  16/26	957	󥹲ϩޤɽФϩǡϲϩΣ	Sensing or reading circuits; Data output circuits [7]
G11C  16/26 100 \	4	4	5B225	G11C  16/26	1321	ü⡼ɤˤɽФ	reading in a special mode
G11C  16/26 110 \	4	4	5B225	G11C  16/26	292	Хåե𤷤ɽФ	reading through buffer memory
G11C  16/26 120 \	4	4	5B225	G11C  16/26	271	ήӷ󥹲ϩ	Current comparison type sensing circuits
G11C  16/26 130 \	4	4	5B225	G11C  16/26	257	ħ	characterised by source line control
G11C  16/26 140 \	4	4	5B225	G11C  16/26	406	ϲϩ	Output circuits
G11C  16/28  \	4	4	5B225	G11C  16/28	863	ư󥷥󥰤ޤϥե󥹡ѤΡ㡥ߡΣ	using differential sensing or reference cells, e.g. dummy cells [7]
G11C  16/30  \	3	3	5B225	G11C  16/30	956	϶ϩΣ	Power supply circuits [7]
G11C  16/30 100 \	4	4	5B225	G11C  16/30	875	Űȯϩ	High voltage generation circuits
G11C  16/30 110 \	4	4	5B225	G11C  16/30	141	Űȯϩ	Negative voltage generation circuits
G11C  16/30 120 \	4	4	5B225	G11C  16/30	456	ŰĴϩ	Voltage adjustment circuits
G11C  16/32  \	3	3	5B225	G11C  16/32	466	ߥ󥰲ϩΣ	Timing circuits [7]
G11C  16/34  \	3	3	5B225	G11C  16/34	3	ץߥ󥰾֤ηꡤ㡥ŰߤޤԽʬʽߡƥ󥷥Σ	Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention [7]
G11C  16/34 100 \	4	4	5B225	G11C  16/34	4	ꥻŰμ«ޤõޤϲߥΥڥޤϥꥫХ	Convergence or correction of memory cell threshold voltages; Repair or recovery of overdeleted or excessively written cells
G11C  16/34 103 \	5	5	5B225	G11C  16/34	286	õ٥ե˸Τ줿õ줿ԴȯꥻΥꥫХϩޤˡ̾ϡȥեȡɥץߥ󥰥ƥåפˤ	Circuits or methods to recover overdeleted nonvolatile memory cells detected during deletion verification, usually by means of a "soft" programming step
G11C  16/34 106 \	5	5	5B225	G11C  16/34	9	߸˸Τ줿ߤ줿ԴȯꥻΥꥫХϩޤˡ̾ϡȥեȡɾõƥåפˤ	Circuits or methods to recover excessively written nonvolatile memory cells detected during writing verification, usually by means of a "soft" deletion step
G11C  16/34 110 \	4	4	5B225	G11C  16/34	25	ǥɻߤޤɾǥ֤줿ǡΥեå	Disturbance prevention or evaluation; Refreshing of disturbed memory data
G11C  16/34 113 \	5	5	5B225	G11C  16/34	25	ǥ֤¤륹ƥåפʤԴȯꥻɽФޤϽߥǥ֤ɾϩޤˡ	Circuits or methods to evaluate read or write disturbance in nonvolatile memory cells, without steps for mitigating disturbance
G11C  16/34 116 \	5	5	5B225	G11C  16/34	841	ܥ뤬ɽФޤϽߤ줿Υǥ֤ɻߤޤϼϩޤˡ	Circuits or methods to prevent or mitigate disturbance of the state of a memory cell when neighbouring cells are read or written
G11C  16/34 120 \	5	5	5B225	G11C  16/34	696	ǥ֤줿Դȯꥻ롤㡥񤭹ޤ줿֤ȤɽФ뤬ͤ߸ͤ꾮ޤϾõ줿֤Ȥɤ߽Ф뤬ͤõͤ礭ꥻ롤򸡽ФեåߤޤϾõˤǥ֤ȿžϩޤˡ	Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still are read as written state but with threshold less than the write verify threshold or read as deleted state but with threshold greater than the deletion verification threshold, and to reverse the disturbance via a refreshing writing or deleting step
G11C  16/34 123 \	4	4	5B225	G11C  16/34	7	ŬʽߤޤϾõ򸡾ڤ뤿	Arrangements for verifying correct writing or deletion
G11C  16/34 126 \	5	5	5B225	G11C  16/34	1	Ŭʾõ򸡾ڤ뤿ޤϲõ򸡽Ф뤿	Arrangements for verifying correct deletion or for detecting overdeleted cells
G11C  16/34 130 \	6	6	5B225	G11C  16/34	562	ԴȯꥻŬڤʾõ򸡾ڤ뤿βϩޤˡ	Circuits or methods to verify correct deletion of nonvolatile memory cells
G11C  16/34 133 \	6	6	5B225	G11C  16/34	155	õ줿Դȯꥻ򸡽Ф뤿βϩޤˡ̾Ͼõں˸Ф	Circuits or methods to detect overdeleted nonvolatile memory cells, usually during deletion verification
G11C  16/34 136 \	5	5	5B225	G11C  16/34	2	Ŭʽߤ򸡾ڤ뤿Τޤϲߥ򸡽Ф뤿	Arrangements for verifying correct writing or for detecting excessively written cells
G11C  16/34 140 \	6	6	5B225	G11C  16/34	1415	ԴȯꥻŬڤʽߤ򸡾ڤϩޤˡ	Circuits or methods to verify correct writing of nonvolatile memory cells
G11C  16/34 143 \	6	6	5B225	G11C  16/34	119	ߤ줿Դȯꥻ򸡽Фϩޤˡ̾Ͻ߸ں˸Ф	Circuits or methods to detect excessively written nonvolatile memory cells, usually during writing verification
G11C  16/34 146 \	5	5	5B225	G11C  16/34	2	õޤϲߤɻߡ㡥õޤϽߤκθڤˤ	Prevention of overdeletion or excessive writing, e.g. by verifying whilst deleting or writing
G11C  16/34 150 \	6	6	5B225	G11C  16/34	90	õʹԴȯꥻŬڤʾõ򸡾ڤϩޤˡ㡥ήήγϤޤߤ򸡽ФнϤõνλѤ뤳Ȥˤ	Circuits or methods to verify correct deletion of nonvolatile memory cells whilst deletion is in progress, e.g. by detecting onset or cessation of current flow in cells and using the detection output to terminate deletion
G11C  16/34 153 \	6	6	5B225	G11C  16/34	56	Դȯꥻβõɻߤϩޤˡ㡥ήήγϤޤߤ򸡽ФнϤõνλѤ뤳Ȥˤ	Circuits or methods to prevent overdeletion of nonvolatile memory cells, e.g. by detecting onset or cessation of current flow in cells and using the detection output to terminate deletion
G11C  16/34 156 \	6	6	5B225	G11C  16/34	113	߿ʹԴȯꥻŬڤʽߤ򸡾ڤϩޤˡ㡥ήήγϤޤߤ򸡽ФнϤߤνλѤ뤳Ȥˤ	Circuits or methods to verify correct writing of nonvolatile memory cells whilst writing is in progress, e.g. by detecting onset or cessation of current flow in cells and using the detection output to terminate writing
G11C  16/34 160 \	6	6	5B225	G11C  16/34	12	Դȯꥻβߤɻߤϩޤˡ㡥ήήγϤޤߤ򸡽ФнϤߤνλѤ뤳Ȥˤ	Circuits or methods to prevent excessive writing, e.g. by detecting onset or cessation of current flow in cells and using the detection output to terminate writing
G11C  16/34 163 \	4	4	5B225	G11C  16/34	592	ƥ󥷥󡤤ޤפɾ뤿֡㡥õ򥫥Ȥ뤳Ȥˤ	Arrangements for evaluating degradation, retention or wearout, e.g. by counting deletion cycles
G11C  16/34 166 \	5	5	5B225	G11C  16/34	654	ԴȯţУңϣͤޤϣţţУңϣͥǥХפ򸡽Фޤ٤餻ϩޤˡ㡥õޤϹ򥫥ȤʣΥΰ缡ޤϽ۴Ū˻Ѥ뤳Ȥˤ	Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of deletion or update cycles, by using multiple memory areas serially or cyclically
G11C  17/00  \	0	0	5B225	G11C  17/00	2049	٤ץǽɽФѥꡨȾʵŪ֡㡥ưǺؤǽʾ󥫡ɡΣ	Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards [2006.01]
G11C  17/02  \	1	1	5B225	G11C  17/02	380	ŪޤͶƳŪǻҤѤΡʣǣãͥˡΣ	using magnetic or inductive elements (G11C17/14 takes precedence) [2, 5]
G11C  17/04  \	1	1	5B225	G11C  17/04	100	ŪǻҤѤΡʣǣãǣãͥˡΣ	using capacitive elements (G11C17/06, G11C17/14 take precedence) [2, 5]
G11C  17/06  \	1	1	5B225	G11C  17/06	1198	ǻҤѤΡʣǣãͥˡΣ	using diode elements (G11C17/14 takes precedence)  [2, 5]
G11C  17/08  \	1	1	5B225	G11C  17/08	9	ȾƳ֤ѤΡ㡥ХݡǻҤѤΡʣǣãǣãͥˡΣ	using semiconductor devices, e.g. bipolar elements (G11C17/06, G11C17/14 take precedence) [5]
G11C  17/10  \	2	2	5B225	G11C  17/10	311	εƤǻҤΤ餫줿֤ˤä¤˷Ρ㡥ޥץǽʣңϣ͡Σ	in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM [5]
G11C  17/10 100 \	3	3	5B225	G11C  17/10	115	Хݡȥ󥸥Ѥ	using bipolar transistors
G11C  17/10 110 \	4	4	5B225	G11C  17/10	37	ղϩ	Auxiliary circuits
G11C  17/12  \	3	3	5B225	G11C  17/12	538	ų̷֤ѤΡΣ	using field-effect devices [5]
G11C  17/12 100 \	4	4	5B225	G11C  17/12	241	ľ³줿ʣεȥ󥸥ͭ륻ǹ	comprising cells having several storage transistors connected in series
G11C  17/12 110 \	4	4	5B225	G11C  17/12	79	ϥ쥤	Virtual ground arrays
G11C  17/12 150 \	4	4	5B225	G11C  17/12	867	ղϩ	Auxiliary circuits
G11C  17/12 160 \	5	5	5B225	G11C  17/12	199	ľ³줿ʣεȥ󥸥ͭ륻ǹ륢쥤Ѥμղϩ	Auxiliary circuits for arrays comprising cells having several storage transistors connected in series
G11C  17/12 170 \	5	5	5B225	G11C  17/12	59	ϥ쥤Ѥμղϩ	Auxiliary circuits for virtual ground arrays
G11C  17/14  \	1	1	5B225	G11C  17/14	15	εƤǻҤξ֤ʵפѤ뤳ȤˤäϢ󥯤ŪꡤǤޤѹ뤳ȤˤΡ㡥Уңϣ͡Σ	in which contents are determined by selectively establishment, break, or modification of connecting links due to permanent alteration in the state of coupling elements, e.g. PROM [5]
G11C  17/14 100 \	2	2	5B225	G11C  17/14	3	졼ǲǽʥ󥯤Ѥ	using laser-fusible links
G11C  17/14 110 \	2	2	5B225	G11C  17/14	19	饤ȥ󥹥ꡤ㡡ղåӥåȤ˽ߤԤȤǥƤѹ	Write once memory, e.g. allowing changing of memory contents by writing additional bits
G11C  17/16  \	2	2	5B225	G11C  17/16	147	ŵŪǲǽʥ󥯤ѤΡΣ	using electrically-fusible links [5]
G11C  17/16 100 \	3	3	5B225	G11C  17/16	11	񹳤Ѳ褦ŵŪ˥ץवꥻ롤㡥ҥ塼ҥ塼Ƴ̤Ƴ̡Ƴ̤Ƴ֤̾ؤѹȤꡤʣʳ˥ץǤΡ񹳥ॢǻҤѤǥ뵭֡ǣã	Electrically programmed memory cells to induce a change in resistance, e.g., to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses (digital storage devices using resistive random access memory elements: G11C13/00, 200)
G11C  17/18  \	2	2	5B225	G11C  17/18	87	ղϩ㡥ؤνѡΣ	Auxiliary circuits, e.g. for writing into memory [2006.01]
G11C  19/00  \	0	0	5B074	G11C  19/00	2877	󤬥ƥå׷ǰưǥ뵭֡㡥եȡ쥸Σ	Digital stores in which the information is moved stepwise, e.g. shift registers [2006.01]
G11C  19/02  \	1	1	5B074	G11C  19/02	77	ǻҤѤΡʣǣãͥˡΣ	using magnetic elements (G11C 19/14 takes precedence) [2]
G11C  19/04  \	2	2	5B074	G11C  19/04	22	Ĥιޤϼ롼פͭ륳ѤΡΣ	using cores with one aperture or magnetic loop [2]
G11C  19/06  \	2	2	5B074	G11C  19/06	18	¿ιޤϼ롼פͭ빽¤ѤΡ㡥ȥ󥹥ե饯Σ	using structures with a number of apertures or magnetic loops, e.g. transfluxors [2]
G11C  19/08  \	2	2	5B002	G11C  19/08	257	ʿ칽¤ѤΡΣ	using thin films in plane structure [2]
G11C  19/10  \	2	2	5B074	G11C  19/10	0	åɾѤΡĥˤΡΣ	using thin films on rods; with twistors [2]
G11C  19/12  \	1	1	5B074	G11C  19/12	1	ϩͶƳǻҤѤΡΣ	using non-linear reactive devices in resonant circuits [2]
G11C  19/14  \	1	1	5B074	G11C  19/14	3	ǽưǻҡ㡥ŴɡȾƳǻҡȷ礷ǻҤѤΡʣǣãͥˡΣ	using magnetic elements in combination with active elements, e.g. discharge tubes, semiconductor elements [2]
G11C  19/18  \	1	1	5B074	G11C  19/18	11	ơμǻҤȤƥѥѤΡΣ	using capacitors as main elements of the stages [2]
G11C  19/18 100 \	2	2	5B074	G11C  19/18	0	ȾƳǻҤȷ礹Ρ㡥Хݡȥ󥸥	combined with semicoductor element,  e.g. bipolar transistor,  diode
G11C  19/18 110 \	3	3	5B074	G11C  19/18	13	ų̥ȥ󥸥ȷ礹Ρ㡥ͣϣӡݣƣţ	combined with field effect transistor, e.g. MOS-FET
G11C  19/18 115 \	4	4	5B074	G11C  19/18	7	ĤΥѥˤĤĤΥȥ󥸥ѤΡ㡥Хĥ졼եȥ쥸	using only one transistor for one capacitor, e.g.  Bucket relay shift register
G11C  19/18 120 \	3	3	5B074	G11C  19/18	5	¿Υեȥ쥸㡥ߥ󥰡ϲϩʣƣɣƣϡǣƣ̣ɣƣϡǣƣ	formation of many shift register, e.g. regeneration, timing, input/output circuit (FIFO G06F5/06; LFO G06F7/78)
G11C  19/20  \	1	1	5B074	G11C  19/20	9	ŴɤѤΡʣǣãͥˡΣ	using discharge tubes (G11C 19/14 takes precedence) [2]
G11C  19/28  \	1	1	5B074	G11C  19/28	597	ȾƳǻҤѤΡʣǣãǣãͥˡΣ	using semiconductor elements (G11C 19/14 takes precedence) [2]
G11C  19/28 100 \	2	2	5B074	G11C  19/28	19	˳ؤŲѤΡ㡥Ųٷǻҡʣããġ	carge storage in space charge layer, e.g. charge coupled device (CCD)
G11C  19/28 105 \	3	3	5B074	G11C  19/28	9	ղϩ㡥ʤ˽ߡǽʤɤ߽ФΤ	peripheral circuit, e.g. write in first layer and read out from last layer
G11C  19/28 120 \	2	2	5B074	G11C  19/28	9	¿Υեȥ쥸ʣƣɣƣϡǣƣ̣ɣƣϡǣƣ	formation of many shift register, e.g. regeneration, timing, input/output circuit (FIFO G06F5/06; LFO G06F7/78)
G11C  19/28 200 \	2	2	5B074	G11C  19/28	44	ХݡƣƲϩ	bipolar FF circuit
G11C  19/28 210 \	2	2	5B074	G11C  19/28	743	ƣţԣƣƲϩ	FETFF circuit
G11C  19/28 220 \	2	2	5B074	G11C  19/28	28	Хݡžȷ	bipolar transfer gate type
G11C  19/28 230 \	2	2	5B074	G11C  19/28	2005	ƣţžȷ	FET transfer gate type
G11C  19/28 240 \	2	2	5B074	G11C  19/28	14	ȥͥ	tunnel diode
G11C  19/30  \	1	1	5B074	G11C  19/30	27	ץȡ쥯ȥ˥֡ʤŵŪޤϸŪ˷礵줿ͤӸŵ֤ѤΡΣ	using opto-electronic devices, i.e. light-emitting and photoelectric devices electrically- or optically-coupled [2]
G11C  19/32  \	1	1	5B074	G11C  19/32	15	ĶƳǻҤѤΡΣ	using super-conductive elements [2]
G11C  19/34  \	1	1	5B074	G11C  19/34	3	ʾΰۤʤ֤ͭ뵭ǻҤѤΡ㡥ŰˤΡήˤΡˤΡȿˤΡΣ	using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency [7]
G11C  19/36  \	2	2	5B074	G11C  19/36	2	ȾƳǻҤѤΡΣ	using semiconductor elements [7]
G11C  19/38  \	1	1	5B074	G11C  19/38	14	󼡸Ρ㡥ʿȿľ˾󤬰ư륷եȥ쥸Σ	two-dimensional [2D], e.g. horizontal and vertical shift registers[2006.01]
G11C  21/00  \	0	0	5B074	G11C  21/00	177	󤬽۴ĤΥǥ뵭֡ʥƥå׷ΤΣǣã	Digital stores in which the information circulates (stepwise G11C 19/00)
G11C  21/02  \	1	1	5B074	G11C  21/02	39	ŻҵŪٱ㡥䥿󥯡Ѥ	using electromechanical delay lines, e.g. using a mercury tank
G11C  23/00  \	0	0	5B074	G11C  23/00	24	ŪʬΰưˤäƵԤʤ碌뤳ȤħȤǥ뵭֡㡥ܡѤΡΤεǻҡΣ	Digital stores characterised by movement of mechanical parts to effect storage, e.g. using balls; Storage elements therefor [2006.01]
G11C  25/00  \	0	0	5B067	G11C  25/00	12	ήΤѤħȤǥ뵭֡Τεǻ	Digital stores characterised by the use of flowing media; Storage elements therefor
G11C  27/00  \	0	0	5B066	G11C  27/00	1044	ŵŪʥ֡㡥ֻͤ򵭲뤿Τ	Electric analogue stores, e.g. for storing instantaneous values
G11C  27/00 200 \	1	1	5B066	G11C  27/00	93	ԴȯŲѤȼΡ㡥ưȤޤϣͣΣϣӾΤ	with non-volatile charge storage, e.g. on floating gate or MNOS
G11C  27/02  \	1	1	5B066	G11C  27/02	93	Сݻ֡ʣǣãͥˡΣ	Sample-and-hold arrangements (G11C 27/04 takes precedence) [2006.01]
G11C  27/02 100 \	2	2	5B066	G11C  27/02	3	ǻҤѤ	using a magnetic memory element
G11C  27/02 200 \	2	2	5B066	G11C  27/02	4	ǻҤѤΡʣǣãͥ	using a capacitive memory element (G11C27/04 takes precedence)
G11C  27/02 210 \	3	3	5B066	G11C  27/02	139	ԡۡɲϩޤΡʸήޤϥѥ륹Υԡͤ¬ǣң	including peak hold circuits (measurement of peak values of alternate currents or pulses; G01R19/04)
G11C  27/02 220 \	3	3	5B066	G11C  27/02	80	Υå󥰼ʡϩˤ	using specific switching measures or form of circuits
G11C  27/02 230 \	4	4	5B066	G11C  27/02	94	ɥåѤ	using diode switches
G11C  27/02 240 \	4	4	5B066	G11C  27/02	193	ȥ󥸥åѤ	using transistor switches
G11C  27/02 245 \	5	5	5B066	G11C  27/02	137	ưȥ󥸥ФѤ	using  a pair of differential transistors
G11C  27/02 250 \	4	4	5B066	G11C  27/02	0	˴Ϣ	related to amplifiers
G11C  27/02 255 \	5	5	5B066	G11C  27/02	222	鵢ԥ롼פı黻Ѥ	using operation amplifiers with negative return loop
G11C  27/02 260 \	4	4	5B066	G11C  27/02	26	ή⡼ɲϩ㡥åȥȥ	Current mode circuits, e.g. switched current memories
G11C  27/02 310 \	3	3	5B066	G11C  27/02	114	ǽˤħդ	characterised by functions
G11C  27/02 320 \	4	4	5B066	G11C  27/02	96	˴ؤ	related to the characteristics of input and output
G11C  27/02 330 \	4	4	5B066	G11C  27/02	199	å󥰻եåȤνΤΤ	for removing switching noises/offset
G11C  27/02 340 \	4	4	5B066	G11C  27/02	95	꡼ɥեкΤΤ	for countermeasures against leakage/drift
G11C  27/02 350 \	4	4	5B066	G11C  27/02	108	®Τѷ㡥ʣΥץۡɲϩߤưΡʣǣãͥ	Transformation for acceleration, e.g. operating a plurality of sample hold circuits alternately (G11C27/02, 220 takes precedence)
G11C  27/04  \	1	1	5B063	G11C  27/04	1283	եȥ쥸Σ	Shift registers [2006.01]
G11C  29/00  \	0	0	5L206	G11C  29/00	308	ΤưΤε֤ΥåХޤϥե饤ưε֤ΥƥȡΣ	Checking stores for correct operation; Testing stores during standby or offline operation [1, 8]
G11C  29/00 401 \	1	1	5L206	G11C  29/00	118	ꥢˤ	in serial memories
G11C  29/00 402 \	1	1	5L206	G11C  29/00	397	ϥ٥ΤΡʤףӣɡ¤λӹΤΤΣȣ̣	at wafer scale level, i.e. WsI (for test and configuration during manufacture H01L21/66 )
G11C  29/00 404 \	1	1	5L206	G11C  29/00	2370	ڥޤϺƹѤθξΥޥ	Masking faults in memories by using spares or by reconfiguring
G11C  29/00 406 \	2	2	5L206	G11C  29/00	417	ղϩִ뤳ȤˤΡ㡥ξ㤷ΤѤ륹ڥŰǥޤϥ󥹥	by replacing auxiliary circuits, e.g. spare voltage generators, decoders or sense amplifiers, to be used instead of defective ones
G11C  29/00 408 \	2	2	5L206	G11C  29/00	260	Ŭִ르ꥺȶѤ	with optimized replacement algorithms
G11C  29/00 410 \	2	2	5L206	G11C  29/00	343	ťѤΡ㡥ťԡѤ	using duplex memories, i.e. using dual copies
G11C  29/00 412 \	2	2	5L206	G11C  29/00	710	ɥ쥹ѴޤѹѤ	using address translation or modifications
G11C  29/00 414 \	3	3	5L206	G11C  29/00	364	åɥơȥǥΤ	in solid state disks
G11C  29/00 416 \	2	2	5L206	G11C  29/00	1549	ץޥ֥ǥХѤ	using programmable devices
G11C  29/00 418 \	3	3	5L206	G11C  29/00	554	ĹǥȤ߹碌	combined in a redundant decoder
G11C  29/00 420 \	3	3	5L206	G11C  29/00	19	ִΥեåԤΡ㡥ģң	with refresh of replacement cells, e.g. in DRAMs
G11C  29/00 422 \	3	3	5L206	G11C  29/00	8	Ĺץߥ󥰥	with redundancy programming schemes
G11C  29/00 424 \	4	4	5L206	G11C  29/00	4	Ūʥҥ塼ѤΡʥҥ塼Ѥ̣ǣã	using a fuse hierarchy (for memories using fuses in general G11C17/16 )
G11C  29/00 426 \	4	4	5L206	G11C  29/00	399	ԴȯޤϥåѤΡʾõǽʥץǽʥꥻ̣ǣã	using non-volatile cells or latches (erasable programmable memory cells in general G11C17/00 )
G11C  29/00 428 \	3	3	5L206	G11C  29/00	640	ɤ줿쥤	with improved layout
G11C  29/00 454 \	3	3	5L206	G11C  29/00	53	Ϥκ︺	with reduced power consumption
G11C  29/00 456 \	4	4	5L206	G11C  29/00	297	ξ㤷ǤڤΥ	with disconnection of faulty elements
G11C  29/00 458 \	3	3	5L206	G11C  29/00	203	ĹִΤΥ륳	with roll call arrangements for redundant substitutions
G11C  29/00 460 \	3	3	5L206	G11C  29/00	688	ξ㤷ڥִ	with substitution of defective spares
G11C  29/00 462 \	3	3	5L206	G11C  29/00	15	ɤ줿֤ޤϰ	with improved access time or stability
G11C  29/00 464 \	4	4	5L206	G11C  29/00	250	ϩٱ뤳Ȥˤ	by introducing a delay in a signal path
G11C  29/00 466 \	4	4	5L206	G11C  29/00	85	ǥΥơʬ䤹뤳Ȥˤ	by splitting the decoders in stages
G11C  29/00 468 \	4	4	5L206	G11C  29/00	432	ʤˤƾĹ򤹤	by choosing redundant lines at an output stage
G11C  29/00 470 \	4	4	5L206	G11C  29/00	195	ܥå󥰤ˤ	by adjacent switching
G11C  29/00 472 \	2	2	5L206	G11C  29/00	67	ꥢ륢ΤΡ㡥եȥ쥸ããĤޤϥХ֥	in serial access memories, e.g. shift registers, CCDs, bubble memories
G11C  29/00 474 \	2	2	5L206	G11C  29/00	9	ʬʥˤ	with partially good memories
G11C  29/00 476 \	3	3	5L206	G11C  29/00	339	Ĥθξ㤷ǥХ򡤺︺줿̡㡥Ⱦʬ̡ͭȤѤ	using a single defective memory device with reduced capacity, e.g. half capacity
G11C  29/00 478 \	3	3	5L206	G11C  29/00	870	ʣθξ㤷Ϣ³ɥ쥹ϰϤͿ褦Ȥ߹碌Ρ㡥ĤΥǥХ¾ΥǥХˤξ㤷֥åִ󥰥֥å󶡤	combining plural defective memory devices to provide a contiguous address range, e.g. one device supplies working blocks to replace defective blocks in another device
G11C  29/02  \	1	1	5L206	G11C  29/02	1002	ξ㤷ղϩθФޤϤΰ֤Σ	Detection or location of defective auxiliary circuits, e.g. defective refresh counters [8]
G11C  29/02 100 \	2	2	5L206	G11C  29/02	308	Űޤήˤ	in voltage or current generators
G11C  29/02 110 \	2	2	5L206	G11C  29/02	604	ɡϲϩˤ	in I/O circuitry
G11C  29/02 120 \	2	2	5L206	G11C  29/02	12	åޤϥߥ󥰲ϩˤ	in clock generator or timing circuitry
G11C  29/02 130 \	2	2	5L206	G11C  29/02	310	ǥˤ	in decoders
G11C  29/02 140 \	2	2	5L206	G11C  29/02	1447	ˤ	in signal lines
G11C  29/02 150 \	2	2	5L206	G11C  29/02	14	󥹥פˤ	in sense amplifiers
G11C  29/02 160 \	2	2	5L206	G11C  29/02	0	ҥ塼ˤ	in fuses
G11C  29/02 170 \	2	2	5L206	G11C  29/02	23	Ŭޤϥѥ᡼Υȥߥ󥰤ȼ	with adaption or trimming of parameters
G11C  29/04  \	1	1	5L206	G11C  29/04	2048	ξ㤷ǻҤθФޤϤΰ֤Σ	Detection or location of defective memory elements [8]
G11C  29/06  \	2	2	5L206	G11C  29/06	708	®Σ	Acceleration testing [8]
G11C  29/08  \	2	2	5L206	G11C  29/08	911	ǽ㡥եåλѥ󡦥եƥȡΣУϣӣԡϡޤʬƥȡΣ	Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing [8]
G11C  29/10  \	3	3	5L206	G11C  29/10	1	ƥȥ르ꥺࡤ㡥ꥹΣͣӣϥ르ꥺࡨƥȥѥ㡥åܡɥѥΣ	Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns [8]
G11C  29/10 100 \	4	4	5L206	G11C  29/10	184	ƥȥѥ	Test patterns
G11C  29/10 110 \	5	5	5L206	G11C  29/10	301	ѥħΤ	having characteristic in pattern generation
G11C  29/10 120 \	6	6	5L206	G11C  29/10	74	åܡɥѥ	Checkerboard patterns
G11C  29/10 130 \	6	6	5L206	G11C  29/10	29	ѥ	Random patterns
G11C  29/10 140 \	6	6	5L206	G11C  29/10	42	ɥ쥹	generate from address
G11C  29/10 150 \	5	5	5L206	G11C  29/10	2	ɥ쥹ϥߥ󥰵Υ	Address humming distance
G11C  29/10 160 \	5	5	5L206	G11C  29/10	51	ɥ쥹Ѵ	Address conversion
G11C  29/12  \	3	3	5L206	G11C  29/12	3528	ΤȤ߹֡㡥Ȥ߹߼ʥƥȡΣ£ɣӣԡϡΣ	Built-in arrangements for testing, e.g. built-in self testing [BIST] [8]
G11C  29/14  \	4	4	5L206	G11C  29/14	5	ǡμ»ܡ㡥ƥȥ⡼ɤΥǥΣ	Implementation of control logic, e.g. test mode decoders [8]
G11C  29/16  \	5	5	5L206	G11C  29/16	23	ޥץΥ˥åȤѤΡ㡥ơȥޥΣ	using microprogrammed units, e.g. state machines [8]
G11C  29/18  \	4	4	5L206	G11C  29/18	14	ɥ쥹֡˥뤿֡㡥ɥ쥹ϩκΣ	Address generation devices; Devices for accessing memories, e.g. details of addressing circuits [8]
G11C  29/18 100 \	5	5	5L206	G11C  29/18	137	ɥ쥹ǥ	Address decoder
G11C  29/18 120 \	5	5	5L206	G11C  29/18	27	ɥ쥹Ѵޤϥޥåԥ󥰡㡥ʪɥ쥹Ѵ	Address conversion or mapping, i.e. logical to physical address
G11C  29/20  \	5	5	5L206	G11C  29/20	35	󥿤ޤեɥХåեȥ쥸Σ̣ƣӣҡϤѤΡΣ	using counters or linear-feedback shift registers [LFSR] [8]
G11C  29/22  \	5	5	5L206	G11C  29/22	60	ꥢإΡΣ	Accessing serial memories [8]
G11C  29/24  \	5	5	5L206	G11C  29/24	157	ŪʥإΡ㡥ߡޤϾĹΣ	Accessing extra cells, e.g. dummy cells or redundant cells [8]
G11C  29/26  \	5	5	5L206	G11C  29/26	423	ޥץ륢쥤إΡʣǣãͥˡΣ	Accessing multiple arrays (G11C29/24 takes precedence) [8]
G11C  29/26 100 \	6	6	5L206	G11C  29/26	513	Ʊƥ	Concurrent test
G11C  29/28  \	6	6	5L206	G11C  29/28	7	¸طΤޥץ륢쥤㡥ޥӥåȤĥ쥤Σ	Dependent multiple arrays, e.g. multi-bit arrays [8]
G11C  29/30  \	5	5	5L206	G11C  29/30	46	󥰥륢쥤إΡΣ	Accessing single arrays [8]
G11C  29/32  \	6	6	5L206	G11C  29/32	20	ꥢ륢ƥȡΣ	Serial access; Scan testing [8]
G11C  29/32 100 \	7	7	5L206	G11C  29/32	379		scan chain
G11C  29/34  \	6	6	5L206	G11C  29/34	99	ޥӥåȤƱ˥ΡΣ	Accessing multiple bits simultaneously [8]
G11C  29/36  \	4	4	5L206	G11C  29/36	367	ǡ֡㡥ǡѴΣ	Data generation devices, e.g. data inverters [8]
G11C  29/38  \	4	4	5L206	G11C  29/38	3	֡Σ	Response verification devices [8]
G11C  29/40  \	5	5	5L206	G11C  29/40	36	̵ѤѤΡΣ	using compression techniques [8]
G11C  29/42  \	5	5	5L206	G11C  29/42	210	ΣţãáϤޤϥѥƥåѤΡΣ	using error correcting codes [ECC] or parity check [8]
G11C  29/44  \	4	4	5L206	G11C  29/44	41	ɽޤϼ̡㡥ΤΤΡΣ	Indication or identification of errors, e.g. for repair [8]
G11C  29/44 100 \	5	5	5L206	G11C  29/44	1106	ʽΤΤ	for self repair
G11C  29/44 110 \	5	5	5L206	G11C  29/44	331	ƥȷ̡ʼǡåףɣĤޤϽȥ졼	Internal storage of test result, quality data, chip identification, repair information
G11C  29/46  \	4	4	5L206	G11C  29/46	638	ƥȥȥꥬåΣ	Test trigger logic [8]
G11C  29/48  \	3	3	5L206	G11C  29/48	633	֤γμʤˤäŬŪ֡㡥쥯ȥꥢΣģͣϤѤΡޤϼեϩѤΡΣ	Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths [2006.01]
G11C  29/50  \	2	2	5L206	G11C  29/50	15	ޡ㡥ߥ󥰡ŰޤήΣ	Marginal testing, e.g. race, voltage or current testing [8]
G11C  29/50 100 \	3	3	5L206	G11C  29/50	467	ŰΥޡ	Marginal testing of threshold voltage
G11C  29/50 110 \	3	3	5L206	G11C  29/50	4	ԡ󥹤Υޡ	Marginal testing of impedance
G11C  29/50 120 \	3	3	5L206	G11C  29/50	156	ߥ󥰤Υޡ	Marginal testing of timing
G11C  29/50 130 \	3	3	5L206	G11C  29/50	4	ƥ󥷥Υޡ	Marginal testing of retention
G11C  29/50 150 \	3	3	5L206	G11C  29/50	151	ŰΥޡ	Marginal testing of voltage
G11C  29/52  \	1	1	5L206	G11C  29/52	1249	ƤݸƤθθСΣ	Protection of memory contents; Detection of errors in memory contents [8]
G11C  29/54  \	1	1	5L206	G11C  29/54	2	ϩ߷פ뤿֡㡥ƥưײ߷סΣģƣԡϥġΣ	Arrangements for designing test circuits, e.g. design for test [DFT] tools [8]
G11C  29/56  \	1	1	5L206	G11C  29/56	19	ŪΤγ֡㡥ư֡ΣԣšϡΥ󥿡եΣ	External testing equipment for static stores, e.g. automatic test equipment [ATE]; Interfaces therefor [8]
G11C  29/56 100 \	2	2	5L206	G11C  29/56	16	ѥ	Pattern generation
G11C  29/56 105 \	2	2	5L206	G11C  29/56	172	顼ʬϡ顼ɽ	Error analysis, representation of errors
G11C  29/56 110 \	2	2	5L206	G11C  29/56	149	ߥ󥰤¦̡åޤƱ	Timing aspects, clock generation, synchronisation
G11C  29/56 135 \	2	2	5L206	G11C  29/56	260		Concurrent test
G11C  29/56 140 \	2	2	5L206	G11C  29/56	156	®	speeding up
G11C  29/56 155 \	2	2	5L206	G11C  29/56	116	̤ΰ	Compressing test results
G11C  99/00  \	0	0	5B066	G11C  99/00	0	Υ֥饹¾Υ롼פʬवʤΣ	Subject matter not provided for in other groups of this subclass [8]
