H03L   1/00  \	0	0	5J106	H03L   1/00	117	ʪŪ͡㡤ϡѲФȯϤΰ경Σ	Stabilisation of generator output against variations of physical values, e.g. power supply [2006.01]
H03L   1/02  \	1	1	5J106	H03L   1/02	625	٤ѲΤߤФΡΣ	against variations of temperature only [3]
H03L   1/04  \	2	2	5J106	H03L   1/04	78	٤˰ݻ뤿ι¤κΣ	Constructional details for maintaining temperature constant [3]
H03L   3/00  \	0	0	5J106	H03L   3/00	252	ȯεưΣ	Starting of generators [3]
H03L   5/00  \	0	0	5J106	H03L   5/00	276	ŰήޤϤμưΣ	Automatic control of voltage, current, or power [3]
H03L   5/02  \	1	1	5J106	H03L   5/02	76	ϤμưΣ	of power [3]
H03L   7/00  \	0	0	5J106	H03L   7/00	1504	ȿޤϰμư桨ƱΣ	Automatic control of frequency or phase; Synchronisation [2006.01]
H03L   7/00 210 \	1	1	5J106	H03L   7/00	496	ʣȯƱͽ	Mutual synchronisation of multiple oscillators, reserved for service
H03L   7/00 220 \	2	2	5J106	H03L   7/00	454	ٱ椹ʤޤ	including a means of controlling the phase shifter or delay line
H03L   7/00 230 \	1	1	5J106	H03L   7/00	191	Ͽ椬Ĵ沽ƤΡʣȣ̣ͥ	input signal being modulated or encoded (H03L7/08 107 takes precedence)
H03L   7/02  \	1	1	5J106	H03L   7/02	501	ưȿǻҤʤȿ̴ѤΡΣ	using a frequency discriminator comprising a passive frequency-determining element [3]
H03L   7/04  \	2	2	5J106	H03L   7/04	73	ȿǻҤʬ󥹤ȥѥ󥹤ʤΡΣ	wherein the frequency-determining element comprises distributed inductance and capacitance [3]
H03L   7/06  \	1	1	5J106	H03L   7/06	857	ȿޤϰå롼פ˲ä࿮ѤΡΣ	using a reference signal applied to a frequency- or phase-locked loop [3]
H03L   7/06 210 \	2	2	5J106	H03L   7/06	758	å롼	Phase lock loop
H03L   7/06 220 \	2	2	5J106	H03L   7/06	297	ʹѤ	using a numeric reference
H03L   7/06 230 \	2	2	5J106	H03L   7/06	436	ȿӤˤΡʣȣ̣ͥ	using frequency comparison (H03L7/06 240 takes precedence.)
H03L   7/06 240 \	2	2	5J106	H03L   7/06	114	ĤμȿŰѴνŰӤ	comparing the output voltages of two frequency voltage converters
H03L   7/07  \	2	2	5J106	H03L   7/07	569	ĤΥ롼פѤΡ㡥ĹåȯΤΤΡΣ	using several loops, e.g. for redundant clock signal generation [2006.01]
H03L   7/08  \	2	2	5J106	H03L   7/08	950	å롼פκΣ	Details of the phase-locked loop [2006.01]
H03L   7/08 102 \	3	3	5J106	H03L   7/08	1494	Ͼ̤ηڸŬ롼סʣȣ̣ͥ	loop adapted to reducing electric power consumption (H03L7/14 takes precedence)
H03L   7/08 105 \	3	3	5J106	H03L   7/08	415	롼׳λѤΤɲŪ濮󶡤뤳ȤŬ롼	loop adapted to providing additional control signal for use at outside of loop
H03L   7/08 107 \	3	3	5J106	H03L   7/08	2358	˴࿮ΥꥫХ꡼ϩ˴ؤ	mainly  involving recovery circuit of standard signal
H03L   7/08 210 \	3	3	5J106	H03L   7/08	1501	У̣̤˴ؤ	related to the PLL input unit
H03L   7/08 220 \	3	3	5J106	H03L   7/08	1125	У̣̤ν˴ؤ	related to the PLL output unit
H03L   7/08 230 \	3	3	5J106	H03L   7/08	364	У̣̤㸺ʤ˴ؤ	related to the means of reducing the constant phase error of PLL
H03L   7/08 240 \	3	3	5J106	H03L   7/08	347	ϿȽϿ̤μȿޤϰطǰƱ뤿ι˴ؤ	related to the configuration for phase synchronisation between the input signal and output signal in a particular frequency-phase correlation
H03L   7/08 250 \	4	4	5J106	H03L   7/08	498	롼˼ȿѴĤ	having a frequency converter in a loop
H03L   7/081  \	3	3	5J106	H03L   7/081	317	ղŪͭΡΣ	provided with an additional controlled phase shifter [5]
H03L   7/081 120 \	4	4	5J106	H03L   7/081	432	ŰޤŸȯѤʤ	not using voltage or power source controlling oscillator
H03L   7/081 140 \	5	5	5J106	H03L   7/081	397	ǥ椵	digitally controlled phase shifer
H03L   7/081 160 \	5	5	5J106	H03L   7/081	451	浪Ӽȿޤϰ긡֤̤Ϥ³Ƥ	controlled phase shifter and frequeny or phase detector being connected to commoon input
H03L   7/081 180 \	5	5	5J106	H03L   7/081	125	郎Ƥ̩ٱޤϰꥷեȼʤʤ	phase shifter consist of rough and precise delay or pase sft means
H03L   7/083  \	3	3	5J106	H03L   7/083	89	࿮椬ղŪľȯ˲äΡΣ	the reference signal being additionally directly applied to the generator [2006.01]
H03L   7/085  \	3	3	5J106	H03L   7/085	1494	ϿΤޤȤƼȿޤϰ긡֤˴ؤΡʣȣ̣ͥ表ߤΩʣĤοưΰޤϼȿӤ뤿βϩȣģˡΣ	concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal  (H03L 7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D 13/00) [2006.01]
H03L   7/087  \	4	4	5J106	H03L   7/087	1387	롼˾ʤȤ⣲Ĥΰ긡дޤϼȿдȰ긡дѤΡΣ	using at least two phase detectors or a frequency and phase detector in the loop [5]
H03L   7/089  \	4	4	5J106	H03L   7/089	662	åץѥ륹Ϥޤϼȿдʣȣ̣ͥˡΣ	the phase or frequency detector generating up-down pulses(H03L7/087 takes precedence) [5]
H03L   7/089 110 \	5	5	5J106	H03L   7/089	209	ӥήȯ㡥åץѥ륹ˤ椵㡼ݥ	source and sink current generator, e.g. charge pump controlled by up-down pulse
H03L   7/089 130 \	6	6	5J106	H03L   7/089	72	åץѥ륹ˤ椵롤롼ΰۤʤ֤³줿ʤȤ⣲ĤΥήȯޤϾʤȤ⣲ĤΥήȯ	two or more source current generators or two or more sink current generators each connected to different locations of loop and controlled by up-down pulse
H03L   7/089 150 \	6	6	5J106	H03L   7/089	127	ήȯκʣȣ̣ͥ	details of curret generator (H03L7/089 130 takes precedence)
H03L   7/089 160 \	7	7	5J106	H03L   7/089	56	ưåץѥ륹ˤ椵ήȯ	current generator controlled by differential up-down pulse
H03L   7/089 180 \	7	7	5J106	H03L   7/089	36	ޤϥήͤѤǤΡʣȣ̣ͥ	source or sink current value being variables (H03L7/089 160 takes precedence)
H03L   7/091  \	4	4	5J106	H03L   7/091	370	ץ֤Ѥޤϼȿдʣȣ̣ͥˡΣ	the phase or frequency detector using a sampling device(H03L7/087 takes precedence) [5]
H03L   7/093  \	4	4	5J106	H03L   7/093	3123	롼̤ʤȤޤѤΡʣȣ̣ȣ̣ͥˡΣ	using special filtering or amplification characteristics in the loop (H03L7/087 to H03L7/091  take precedence) [5]
H03L   7/095  \	4	4	5J106	H03L   7/095	928	åдѤΡʣȣ̣ͥˡΣ	using a lock detector(H03L7/087 takes precedence) [5]
H03L   7/097  \	4	4	5J106	H03L   7/097	1	ĤμȿŰѴνŰӤӴѤΡΣ	using a comparator for comparing the voltages obtained from two frequency to voltage converters [5]
H03L   7/099  \	3	3	5J106	H03L   7/099	1353	Ȥƥ롼ȯ˴ؤΡΣ	concerning mainly the controlled oscillator of the loop [5]
H03L   7/099 110 \	4	4	5J106	H03L   7/099	171	ǥȯ㡥ȯ˲ʬ郎³ΤʤΡʣȣ̣ͥ表Ƽ򤹤ʤͭȯȣ̣	digital oscillator, e.g. consists of variable frequency divider joined with fixed oscillator (H03L7/099 150 takes precedence, fixed oscillator having means to select from various phases H03L7/081 140)
H03L   7/099 120 \	5	5	5J106	H03L   7/099	499	׿ޤʬ狼ʤ	consist of counter or divider
H03L   7/099 130 \	6	6	5J106	H03L   7/099	148	˥ѥ륹ɲäޤϺ뤿βϩޤ	further including circuit for adding or deleting pulse
H03L   7/099 140 \	5	5	5J106	H03L   7/099	127	ѻ狼ʤ	consist of integrator
H03L   7/099 150 \	4	4	5J106	H03L   7/099	538	ȯ狼ʤȯ	oscillator consist of ring oscillator
H03L   7/099 160 \	5	5	5J106	H03L   7/099	41	ȯˤʣΰ꿮椫飱Ĥο򤹤	selecting one signal among plural phase shifting signal grenerated from ring oscillator
H03L   7/099 170 \	5	5	5J106	H03L   7/099	61	ȯľ³줿ٱǿ椹	controls delay element numbers serially connected to ring oscillator
H03L   7/099 180 \	5	5	5J106	H03L   7/099	7	֤ѤΡʣȣ̣⻲ȡ	using phase interpolation (also refer to H03L7/099 150)
H03L   7/10  \	3	3	5J106	H03L   7/10	553	Ʊμ¤ˤ뤿ΤΡޤϥץ㡼󥸤򹭤뤿ΤΡΣ	for assuring initial synchronisation or for broadening the capture range [3]
H03L   7/10 110 \	4	4	5J106	H03L   7/10	152	롼פ椫ȯɲ濮롼ȯѤΡʣȣ̣ӣȣ̣ͥ	sing additional control signal generated from signal created in loop to control loop oscillator (H03L7/113 and H03L7/187 take precedence)
H03L   7/10 120 \	5	5	5J106	H03L   7/10	106	ɲÿ椬롼ȯľŬѤ	additional signal is applied directly to control loop oscillator
H03L   7/10 130 \	6	6	5J106	H03L   7/10	99	ɲÿ椬ǥ뿮Ǥ	additional signal being digital signal
H03L   7/10 140 \	4	4	5J106	H03L   7/10	1303	롼פǥѥ᡼ޤ椹뤿ˡ롼פγɲÿѤΡʣȣ̣ȣ̣ͥ	using additional signal from outside of loop to establis or coontrol parameter inside loop (H03L7/107, H03L7/187 take precedence)
H03L   7/10 150 \	4	4	5J106	H03L   7/10	21	ȿͳΤȤȯΥꥻå	resetting controlled oscillator when freqency exceeds predetermined limit value
H03L   7/107  \	4	4	5J106	H03L   7/107	421	롼פФƲãؿѤΡ㡥ӰҤĥѥե륿Σ	using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth [5]
H03L   7/107 120 \	5	5	5J106	H03L   7/107	260	㡼ݥפѹ뤳ȤˤΡ㡥ѹ	by altering characteristics of charge pump, e.g. altering gain
H03L   7/107 150 \	5	5	5J106	H03L   7/107	760	롼ץե륿ѹ뤳ȤˤΡ㡥ѹӰҤѹʣȣ̣ͥ	by altering characteristics of loop filter, e.g. altering gain, altering bandwidth (H03L7/107 120 takes precedence)
H03L   7/107 170 \	5	5	5J106	H03L   7/107	168	ޤϼȿμʤѹ뤳ȤˤΡʣȣ̣ͥ	by altering characteristics of phase or frequency detection means (H03L7/107 120 takes precedence)
H03L   7/113  \	4	4	5J106	H03L   7/113	621	ȿ̴ѤΡΣ	using frequency discriminator [5]
H03L   7/12  \	4	4	5J106	H03L   7/12	286	ݰѤΡΣ	using a scanning signal [2006.01]
H03L   7/14  \	3	3	5J106	H03L   7/14	539	ŰޤŰ㲼Ȥȿˤ뤳Ȥμ¤ˤ뤿ΤΡΣ	for assuring constant frequency when supply or correction voltages fail [3]
H03L   7/14 110 \	4	4	5J106	H03L   7/14	4	Ĥȯ֤椹å롼	phase lock loop for controling multiple oscillator in order
H03L   7/14 130 \	4	4	5J106	H03L   7/14	115	å롼פδ࿮ڤ괹뤳Ȥˤ	by switching standard signal of phase lock loop
H03L   7/14 150 \	5	5	5J106	H03L   7/14	57	ڤ괹࿮椬ȯνϿͳ褹	standard signal to be switched originated in output signal of controled oscillator
H03L   7/14 160 \	4	4	5J106	H03L   7/14	159	ȯ濮ǥʤѤΡʣȣ̣ȣ̣ͥ	using digital means generating oscillatot controled signal (H03L7/14 110, H03L7/14 130 take precedence)
H03L   7/14 180 \	5	5	5J106	H03L   7/14	17	ǥʤ׿ޤʬ狼ʤ	digital means coonsist of counter or divider
H03L   7/16  \	2	2	5J106	H03L   7/16	903	Ūʼȿιʤȿޤϰå롼פѤͽ줿¿μȿν˾ΰĤȯΡΣ	Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop [3]
H03L   7/18  \	3	3	5J106	H03L   7/18	1103	롼פʬޤϷ׿ѤΡʣȣ̣ȣ̣ͥˡΣ	using a frequency divider or counter in the loop (H03L 7/20, H03L 7/22 take precedence) [3]
H03L   7/18 103 \	4	4	5J106	H03L   7/18	4	ʬޤϷ׿郎ʬѥ륹ϩ³	dvider or counter being connected to pulse swallow circuit generating frequency-division signal
H03L   7/18 106 \	4	4	5J106	H03L   7/18	36	ʬ郎ʬѻ狼ʤ	frequency divider consist of phase integrator generating ftreqency-division signal
H03L   7/181  \	4	4	5J106	H03L   7/181	27	롼פå뤿˿ͷ׿̤ѤΡַ׿׿Σ	a numerical count result being used for locking the loop, the counter counting during fixed time intervals [5]
H03L   7/183  \	4	4	5J106	H03L   7/183	2129	롼פå뤿˻ֺѤΡʹַ׿ޤϰͤʬʬΣ	a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number [5]
H03L   7/185  \	5	5	5J106	H03L   7/185	660	롼˥ߥѤΡʣȣ̣ȣ̣ͥˡΣ	sing mixer in loop (H03L7/187 - H03L7/195 take precedence) [5]
H03L   7/187  \	5	5	5J106	H03L   7/187	749	롼ŰȯƱĴ뤿μʤѤΡʣȣ̣ȣ̣ͥˡΣ	usig means for coarse tuning voltage-controlled oscillators in loop (H03L7/1891 - H03L7/195 take precedence) [5]
H03L   7/189  \	6	6	5J106	H03L   7/189	181	ƱĴŰȯ뤿ΣġѴޤΡΣ	comprising a D/A converter for generating a coarse tuning voltage [5]
H03L   7/191  \	5	5	5J106	H03L   7/191	33	ֺꤹ뤿ʬޤϷ׿狼龯ʤȤ⣲Ĥΰۤʤ뿮ѤΡʣȣ̣ȣ̣ͥˡΣ	using at least two different signals from the frequency divider or the counter for determining the time difference(H03L7/193, H03L7/195 take precedence) [5]
H03L   7/193  \	5	5	5J106	H03L   7/193	183	ߴΤʬ狼ʤʬޤϷ׿㡥⥸塼ʬΣ	the frequency divider/counter comprising a commutable pre-divider, e.g. a two modulus divider [2006.01]
H03L   7/195  \	5	5	5J106	H03L   7/195	1	롼η׿郎Ĥΰۤʤäʹ֤׿Ρ㡥եåȼȿȯ뤿ΤΡʣȣ̣ͥˡΣ	in which the counter of the loop counts between two different non zero numbers, e.g. for generating an offset frequency  (H03L 7/193 takes precedence) [2006.01]
H03L   7/197  \	4	4	5J106	H03L   7/197	152	롼פå뤿˻ֺѤΡŬѲǽʿʹ֤׿׿ޤŬѲǽʷˤäʬʬ㡥μȿʬΡΣ	a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division [5]
H03L   7/197 120 \	5	5	5J106	H03L   7/197	52	å֤ṳ̂뤿ΤΡʣȣ̣ȣ̣ͥ	for reducing lock time (H03L7/197 140, H03L7/199 take precedence)
H03L   7/197 140 \	5	5	5J106	H03L   7/197	184	μȿʬΤΤ	for frequency division in noninteger
H03L   7/197 160 \	6	6	5J106	H03L   7/197	300	׿ޤʬ椹뤿˰ѻѤ	using phase integrator for controling counter or divider
H03L   7/197 180 \	7	7	5J106	H03L   7/197	2	ޤϥѥ륹ϩѤ	using cycle or pulse removal circuit
H03L   7/199  \	5	5	5J106	H03L   7/199	18	ʬޤϷ׿ΥꥻåȤѤΡ㡥Ʊμ¤ˤ뤿ΤΡΣ	with reset of the frequency divider or the counter, e.g. for assuring initial synchronisation [5]
H03L   7/20  \	3	3	5J106	H03L   7/20	99	ĴȰå롼סʤ뤵줿¿ιĴȴطˤȿΰĤ˥å뤳ȤǤ롼פѤΡʣȣ̣ͥˡΣ	using a harmonic phase-locked loop, i.e. a loop which can be locked to one of a number of harmonically related frequencies applied to it (H03L 7/22 takes precedence) [3]
H03L   7/22  \	3	3	5J106	H03L   7/22	641	İʾΥ롼פѤΡΣ	using more than one loop [3]
H03L   7/23  \	4	4	5J106	H03L   7/23	435	ѥ륹׿ޤʬͭΡΣ	with pulse counters or frequency dividers [5]
H03L   7/23 150 \	5	5	5J106	H03L   7/23	42	Ҽå롼	nested phase lock loop
H03L   7/24  \	1	1	5J106	H03L   7/24	436	࿮椬ȯľܲäΡΣ	using a reference signal directly applied to the generator [3]
H03L   7/26  \	1	1	5J106	H03L   7/26	920	ȿδȤʬҡҤޤϰγҤΥͥ륮٥ѤΡΣ	using energy levels of molecules, atoms, or subatomic particles as a frequency reference [3]
H03L   9/00  \	0	0	5J106	H03L   9/00	1	Υ֥饹¾Υ롼פʬवʤưΣ	Automatic control not provided for in other groups of this subclass [8]
