H10B  10/00  \	0	0	5F083	H10B  10/00	4593	ƥåॢΣӣң֡͡Σ	Static random access memory [SRAM] devices [2023.01]
H10B  10/00 371 \	1	1	5F083	H10B  10/00	530	Хݡ顤ͣϣӰʳΥƥåॢ깽¤	Structures of static random access memories, except bipolar memories, MOS
H10B  10/00 401 \	2	2	5F083	H10B  10/00	81	ܹ緿ޤϣӣɣԥȥ󥸥	Composite or SIT transistor memories
H10B  10/10  \	1	1	5F083	H10B  10/10	490	Хݡ鹽ʤʤӣң֡Σ	SRAM devices comprising bipolar components [2023.01]
H10B  12/00  \	0	0	5F083	H10B  12/00	46	ʥߥåॢΣģң֡͡Σ	Dynamic random access memory [DRAM] devices [2023.01]
H10B  12/00 601 \	1	1	5F083	H10B  12/00	130	ͣϣӥȥ󥸥ѥģң	MOS transistor or DRAMs of a capacitor type
H10B  12/00 611 \	2	2	5F083	H10B  12/00	73	ѥ¤ħΤ	Characterized by the structures of capacitors
H10B  12/00 615 \	3	3	5F083	H10B  12/00	657	ץ졼ʷѥ	Capacitors of a planar type
H10B  12/00 621 \	3	3	5F083	H10B  12/00	86	åѥ	Stacked capacitors
H10B  12/00 621 A	3	0	5F083	H10B  12/00	589	˥եƤ	With fins formed laterally
H10B  12/00 621 B	3	0	5F083	H10B  12/00	1149	̤Ѥ	Using vertical planes
H10B  12/00 621 C	3	1	5F083	H10B  12/00	3067	ȥ졼Ŷˤˤܤ̤ͭΡ㡥饦󷿤ޤϣãգзѥ	With dents in the surfaces of storage electrodes, e.g., capacitors of a crown type or of a CUP type
H10B  12/00 621 Z	3	0	5F083	H10B  12/00	2952	¾Υåѥ㡥ñ㥹åޤϥåγƼѷ	Other stacked capacitors, e.g., simple stacked capacitors or any kinds of alternative  stacked capacitors
H10B  12/00 625 \	3	3	5F083	H10B  12/00	50	ȥѥ	Trench capacitors
H10B  12/00 625 A	3	0	5F083	H10B  12/00	736	Ĥ򥻥ץ졼ȤȤѤ	Using substrates as cell plates
H10B  12/00 625 B	3	0	5F083	H10B  12/00	632	Ĥ򥹥ȥ졼ΡɤȤѤ	Using substrates as storage nodes
H10B  12/00 625 C	3	0	5F083	H10B  12/00	461	ȥ˥ץ졼Ȥȥȥ졼ΡɤơΩߤ	Fixing cell plates and storage nodes respectively independently in trenches
H10B  12/00 625 Z	3	0	5F083	H10B  12/00	400	¾Υȥѥ	Other trench capacitors
H10B  12/00 631 \	3	3	5F083	H10B  12/00	117	˳̤Ѥѥ	Capacitors using depletion layer capacitance
H10B  12/00 651 \	3	3	5F083	H10B  12/00	3488	ѥħΤΡ㡥ħΤ	Characterized by capacitors' insulation films, e.g., characterized by the materials used to manufacture insulation films
H10B  12/00 661 \	3	3	5F083	H10B  12/00	431	¾Υѥ	Other capacitors
H10B  12/00 671 \	2	2	5F083	H10B  12/00	37	ȥ󥸥¤ħΤ	Characterized by the structures of transistors
H10B  12/00 671 A	2	0	5F083	H10B  12/00	731	ķȥ󥸥	Vertical transistors
H10B  12/00 671 B	2	1	5F083	H10B  12/00	862	·ȥ󥸥	Transistors of a groove type
H10B  12/00 671 C	2	0	5F083	H10B  12/00	1358	ӣϣɾ˥ȥ󥸥	With transistors formed on SOIs
H10B  12/00 671 Z	2	0	5F083	H10B  12/00	2434	¾Υȥ󥸥	Other transistors
H10B  12/00 681 \	2	2	5F083	H10B  12/00	37	¾㡥쥤ȡħΤ	Others, e.g., characterized by the layout
H10B  12/00 681 A	2	0	5F083	H10B  12/00	829	Υ쥤ȡ¤ޤϺħΤ	Characterized by the layout, structures or materials used for word lines
H10B  12/00 681 B	2	0	5F083	H10B  12/00	1566	ӥåΥ쥤ȡ¤ޤϺħΤ	Characterized by the layout, structures or materials used for bit lines
H10B  12/00 681 C	2	0	5F083	H10B  12/00	238	ޤŸΥ쥤ȡ¤ޤϺħΤ	Characterized by the layout, structures or materials used for earth wires or power supply lines
H10B  12/00 681 D	2	0	5F083	H10B  12/00	728	ǻʬΥ¤ħΤ	Characterized by element isolation structures
H10B  12/00 681 E	2	0	5F083	H10B  12/00	861	åΤޤϤ˶ᤤ쥤ȥץħΤ	Characterized by the layout plans that specify chips as a whole or nearly as a whole
H10B  12/00 681 F	2	0	5F083	H10B  12/00	2586	ղϩι¤ޤϥ쥤ȤħΤ	Characterized by the structures or the layout of peripheral circuit parts
H10B  12/00 681 G	2	1	5F083	H10B  12/00	577	󥹥פħΤ	Characterized by sense amplifiers
H10B  12/00 681 Z	2	0	5F083	H10B  12/00	329	¾	Others
H10B  12/00 691 \	2	2	5F083	H10B  12/00	653	ưɻߤħΤ	Characterized by the prevention of malfunction
H10B  12/00 801 \	1	1	5F083	H10B  12/00	3682	ͣϣӥȥ󥸥ѥʳΣģң	DRAMs other than MOS transistor or DRAMs of a capacitor type
H10B  12/00 821 \	1	1	5F083	H10B  12/00	43	ͣϣӡ¾Υȥ󥸥ʤģң	DRAMs comprised of other transistors including MOS transistors
H10B  12/00 841 \	1	1	5F083	H10B  12/00	567	Хݡ顤ͣϣӰʳΥʥߥåॢ깽¤	Structures of dynamic random access memories , except bipolar memories, MOS
H10B  12/00 861 \	2	2	5F083	H10B  12/00	57	ܹ緿ޤϣӣɣԥȥ󥸥	Junction or SIT transistor memories
H10B  12/10  \	1	1	5F083	H10B  12/10	58	Хݡ鹽ʤʤģң֡Σ	DRAM devices comprising bipolar components [2023.01]
H10B  20/00  \	0	0	5F083	H10B  20/00	1537	ɤ߽ФѥΣңϣ֡͡Σ	Read-only memory [ROM] devices [2023.01]
H10B  20/00 421 \	1	1	5F083	H10B  20/00	197	Хݡ顤ͣϣӰʳԴȯ	Nonvolatile memories, except bipolar memories, MOS
H10B  20/00 437 \	2	2	5F083	H10B  20/00	1	ܹ緿ޤϣӣɣԥȥ󥸥	Junction or SIT transistor memories
H10B  20/10  \	1	1	5F083	H10B  20/10	422	Хݡ鹽ʤʤңϣ֡Σ	ROM devices comprising bipolar components [2023.01]
H10B  20/20  \	1	1	5F083	H10B  20/20	306	ų̹ʤʤ񤭹߲ǽʣңϣ͡ΣУңϣ֡͡ʣȣ£ͥˡΣ	Programmable ROM [PROM] devices comprising field-effect components (H10B 20/10 takes precedence) [2023.01]
H10B  20/25  \	2	2	5F083	H10B  20/25	845	Τ߽񤭹߲ǽʣңϣ͡ΣϣԣУңϣ֡͡㡥ŵŪǲǽʥ󥯤ѤΡΣ	One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links [2023.01]
H10B  41/00  \	0	0	5F083	H10B  41/00	140	եƥ󥰥ȤޤŵŪõ񤭹߲ǽʣңϣ͡ΣţţУңϣ֡͡Σ	Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates [2023.01]
H10B  41/10  \	1	1	5F083	H10B  41/10	1003	夫鸫쥤ȤħΤΡΣ	characterised by the top-view layout [2023.01]
H10B  41/20  \	1	1	5F083	H10B  41/20	192	֡㡥ۤʤ⤵֤줿롤ħΤΡΣ	characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels[2023.01]
H10B  41/23  \	2	2	5F083	H10B  41/23	22	ۤʤ⤵Υȥɥ쥤ͭΡ㡥ХͥͭΡΣ	with source and drain on different levels, e.g. with sloping channels [2023.01]
H10B  41/27  \	3	3	5F083	H10B  41/27	1201	ľʬޤͥ롤㡥ջͥΣ	the channels comprising vertical portions, e.g. U-shaped channels [2023.01]
H10B  41/30  \	1	1	5F083	H10B  41/30	6331	ꥳΰħΤΡΣ	characterised by the memory core region [2023.01]
H10B  41/35  \	2	2	5F083	H10B  41/35	839	ȥ󥸥ͭΡ㡥ΣΣġΣ	with a cell select transistor, e.g. NAND [2023.01]
H10B  41/40  \	1	1	5F083	H10B  41/40	2076	ղϩΰħΤΡΣ	characterised by the peripheral circuit region [2023.01]
H10B  41/41  \	2	2	5F083	H10B  41/41	113	ΰ˥ȥ󥸥ͭΡ㡥ΣΣġΣ	of a memory region comprising a cell select transistor, e.g. NAND [2023.01]
H10B  41/42  \	2	2	5F083	H10B  41/42	468	ե뤪ӥꥻƱ¤Σ	Simultaneous manufacture of periphery and memory cells [2023.01]
H10B  41/43  \	3	3	5F083	H10B  41/43	195	եȥ󥸥ΤߴޤΡΣ	comprising only one type of peripheral transistor [2023.01]
H10B  41/44  \	4	4	5F083	H10B  41/44	1206	ȥ륲ؤեȥ󥸥ΰȤƤѤΡΣ	with a control gate layer also being used as part of the peripheral transistor [2023.01]
H10B  41/46  \	4	4	5F083	H10B  41/46	447	ȴͶؤեȥ󥸥ΰȤƤѤΡΣ	with an inter-gate dielectric layer also being used as part of the peripheral transistor [2023.01]
H10B  41/47  \	4	4	5F083	H10B  41/47	618	եƥ󥰥ؤեȥ󥸥ΰȤƤѤΡΣ	with a floating-gate layer also being used as part of the peripheral transistor [2023.01]
H10B  41/48  \	4	4	5F083	H10B  41/48	496	ȥͥͶؤեȥ󥸥ΰȤƤѤΡΣ	with a tunnel dielectric layer also being used as part of the peripheral transistor [2023.01]
H10B  41/49  \	3	3	5F083	H10B  41/49	858	ۤʤμեȥ󥸥ޤΡΣ	comprising different types of peripheral transistor [2023.01]
H10B  41/50  \	1	1	5F083	H10B  41/50	730	ȼղϩΰȤδ֤ζΰħΤΡΣ	characterised by the boundary region between the core region and the peripheral circuit region [2023.01]
H10B  41/60  \	1	1	5F083	H10B  41/60	365	ȥ륲ȤɡΰǤΡ㡥ñإݥꥻΣ	the control gate being a doped region, e.g. singlepoly memory cell [2023.01]
H10B  41/70  \	1	1	5F083	H10B  41/70	1903	եƥ󥰥ȤʣιʤǶͭŶˤǤΡΣ	the floating gate being an electrode shared by two or more components [2023.01]
H10B  43/00  \	0	0	5F083	H10B  43/00	99	Ų٥ȥåԥ󥰥ΤޤţţУңϣ֡Σ	EEPROM devices comprising charge-trapping gate insulators [2023.01]
H10B  43/10  \	1	1	5F083	H10B  43/10	587	夫鸫쥤ȤħΤΡΣ	characterised by the top-view layout [2023.01]
H10B  43/20  \	1	1	5F083	H10B  43/20	244	֡㡥ۤʤ⤵֤줿롤ħΤΡΣ	characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels[2023.01]
H10B  43/23  \	2	2	5F083	H10B  43/23	43	ۤʤ⤵Υȥɥ쥤ͭΡ㡥ХͥͭΡΣ	with source and drain on different levels, e.g. with sloping channels [2023.01]
H10B  43/27  \	3	3	5F083	H10B  43/27	2726	ľʬޤͥ롤㡥ջͥΣ	the channels comprising vertical portions, e.g. U-shaped channels [2023.01]
H10B  43/30  \	1	1	5F083	H10B  43/30	2982	ꥳΰħΤΡΣ	characterised by the memory core region [2023.01]
H10B  43/35  \	2	2	5F083	H10B  43/35	627	ȥ󥸥ͭΡ㡥ΣΣġΣ	with cell select transistors, e.g. NAND [2023.01]
H10B  43/40  \	1	1	5F083	H10B  43/40	1769	ղϩΰħΤΡΣ	characterised by the peripheral circuit region [2023.01]
H10B  43/50  \	1	1	5F083	H10B  43/50	876	ȼղϩΰȤδ֤ζΰħΤΡΣ	characterised by the boundary region between the core and peripheral circuit regions [2023.01]
H10B  51/00  \	0	0	5F083	H10B  51/00	35	ͶΥȥ󥸥ޤදͶΥΣƣң֡͡Σ	Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors [2023.01]
H10B  51/10  \	1	1	5F083	H10B  51/10	32	夫鸫쥤ȤħΤΡΣ	characterised by the top-view layout [2023.01]
H10B  51/20  \	1	1	5F083	H10B  51/20	99	֡㡥ۤʤ⤵֤줿롤ħΤΡΣ	characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels[2023.01]
H10B  51/30  \	1	1	5F083	H10B  51/30	977	ꥳΰħΤΡΣ	characterised by the memory core region [2023.01]
H10B  51/40  \	1	1	5F083	H10B  51/40	126	ղϩΰħΤΡΣ	characterised by the peripheral circuit region [2023.01]
H10B  51/50  \	1	1	5F083	H10B  51/50	6	ȼղϩΰȤδ֤ζΰħΤΡΣ	characterised by the boundary region between the core and peripheral circuit regions [2023.01]
H10B  53/00  \	0	0	5F083	H10B  53/00	140	ͶΥꥭѥޤදͶΥΣƣң֡͡Σ	Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors [2023.01]
H10B  53/10  \	1	1	5F083	H10B  53/10	240	夫鸫쥤ȤħΤΡΣ	characterised by the top-view layout [2023.01]
H10B  53/20  \	1	1	5F083	H10B  53/20	105	֡㡥ۤʤ⤵֤줿롤ħΤΡΣ	characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels[2023.01]
H10B  53/30  \	1	1	5F083	H10B  53/30	4271	ꥳΰħΤΡΣ	characterised by the memory core region [2023.01]
H10B  53/40  \	1	1	5F083	H10B  53/40	438	ղϩΰħΤΡΣ	characterised by the peripheral circuit region [2023.01]
H10B  53/50  \	1	1	5F083	H10B  53/50	78	ȼղϩΰȤδ֤ζΰħΤΡΣ	characterised by the boundary region between the core and peripheral circuit regions [2023.01]
H10B  61/00  \	0	0	4M119	H10B  61/00	5830	֡㡥񹳣ң͡Σͣң֡͡Σ	Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices [2023.01]
H10B  63/00  \	0	0	5F083	H10B  63/00	4116	Ѳ֡㡥񹳣ң͡Σңң֡͡Σ	Resistance change memory devices, e.g. resistive RAM [ReRAM] devices [2023.01]
H10B  63/10  \	1	1	5F083	H10B  63/10	1864	Ѳң͡ΣУãң͡Уң֡͡Σ	Phase change RAM [PCRAM, PRAM] devices [2023.01]
H10B  69/00  \	0	0	5F083	H10B  69/00	2617	롼ףȣ£ȣ£ޤʤõǽǥץǽʣңϣ͡ΣţУңϣ֡͡㡥糰ˤõǽǥץǽʣңϣ͡Σգ֣ţУңϣ֡͡Σ	Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B 41/00-H10B 63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices [2023.01]
H10B  80/00  \	0	0	5F037	H10B  80/00	8891	Υ֥饹ޤ롤ʤȤ⣱Ĥε֤롤ʣ֤ΩΡΣ	Assemblies of multiple devices comprising at least one memory device covered by this subclass [2023.01]
H10B  99/00  \	0	0	5F083	H10B  99/00	3141	Υ֥饹¾Υ롼פʬवʤΣ	Subject matter not provided for in other groups of this subclass [2023.01]
H10B  99/00 301 \	1	1	5F083	H10B  99/00	231	ޥȥꥯȾƳ	Matrix semiconductor devices
H10B  99/00 441 \	1	1	5F083	H10B  99/00	1090	Դȯң	Nonvolatile RAMs
H10B  99/00 449 \	1	1	5F083	H10B  99/00	516	ͭ	Organic memories
H10B  99/00 451 \	1	1	5F083	H10B  99/00	3381	¾ȾƳΥ	Other semiconductor memories
H10B  99/00 461 \	1	1	5F083	H10B  99/00	2455	ȾƳΥå	Memories in semiconductor chips
H10B  99/00 471 \	1	1	5F083	H10B  99/00	629	ϩι	Configurations, such as circuit arrangements
H10B  99/00 481 \	1	1	5F083	H10B  99/00	5310	ղϩ	Peripheral circuits
H10B  99/00 491 \	1	1	5F083	H10B  99/00	1118	ưɻ	Prevention of malfunction
H10B  99/00 495 \	1	1	5F083	H10B  99/00	706	⥸塼	Memory modules
