H10D   1/00  \	0	0	5F038	H10D   1/00	1	񹳴ѥޤϥΣ	Resistors, capacitors or inductors[2025.01]
H10D   1/20  \	1	1	5F038	H10D   1/20	1795	Σ	Inductors[2025.01]
H10D   1/40  \	1	1	5F038	H10D   1/40	2	񹳴Σ	Resistors[2025.01]
H10D   1/43  \	2	2	5F038	H10D   1/43	1	Уܹͭ񹳴Σ	Resistors having PN junctions[2025.01]
H10D   1/47  \	2	2	5F038	H10D   1/47	1	Ű̾ɤͭʤ񹳴Σ	Resistors having no potential barriers[2025.01]
H10D   1/47 101 \	3	3	5F038	H10D   1/47	3570		thin film resistance
H10D   1/47 102 \	3	3	5F038	H10D   1/47	2366	Ȼ	diffusive resistance
H10D   1/60  \	1	1	5F038	H10D   1/60	2	ѥΣ	Capacitors[2025.01]
H10D   1/62  \	2	2	5F038	H10D   1/62	3	Ű̾ɤͭ륭ѥΣ	Capacitors having potential barriers[2025.01]
H10D   1/62  A	2	0	5F038	H10D   1/62	138	ѲϩѤ	used for integrated circuits
H10D   1/62  C	2	0	5F038	H10D   1/62	55	ʣѥʣͥ	composite capacitors (A takes precedence)
H10D   1/62  Z	2	0	5F038	H10D   1/62	84	¾Τ	Others
H10D   1/64  \	3	3	5F038	H10D   1/64	19	̥ɡ㡥Х饯Σ	Variable-capacitance diodes, e.g. varactors[2025.01]
H10D   1/64  A	3	0	5F038	H10D   1/64	762	ѲϩѤ	used for integrated circuits
H10D   1/64  H	3	0	5F038	H10D   1/64	265	ĶܹѤ	using super step junctions
H10D   1/64  S	3	0	5F038	H10D   1/64	98	åȥХꥢѤ	using Schottky barriers
H10D   1/64  C	3	0	5F038	H10D   1/64	84	¾ŵŪʤղä	adding other electric means to capacity control
H10D   1/64  Z	3	0	5F038	H10D   1/64	487	¾Τ	Others
H10D   1/66  \	3	3	5F038	H10D   1/66	27	ƳΡΡȾƳι¤Υѥ㡥ͣϣӥѥΣ	Conductor-insulator-semiconductor capacitors, e.g. MOS capacitors[2025.01]
H10D   1/66  A	3	0	5F038	H10D   1/66	4799	ѲϩѤ	used for integrated circuits
H10D   1/66  C	3	0	5F038	H10D   1/66	101	¾ŵŪʤղä	adding other electric means to capacity control
H10D   1/66  Z	3	0	5F038	H10D   1/66	337	¾Τ	Others
H10D   1/68  \	2	2	5F038	H10D   1/68	11322	Ű̾ɤͭʤѥΣ	Capacitors having no potential barriers[2025.01]
H10D   8/00  \	0	0	5F087	H10D   8/00	0	ɡʲ̥ɣȣģȥɣȣģˡΣ	Diodes (variable-capacitance diodes H10D 1/64; gated diodes H10D 12/00)[2025.01]
H10D   8/01  \	1	1	5F087	H10D   8/01	2	¤ޤϽΣ	Manufacture or treatment[2025.01]
H10D   8/01  A	1	0	5F087	H10D   8/01	1240	ήɡ㡥УΥɡУɣΥɡˡˡħΤ	characterized by the manufacturing methods of rectifier diodes, e.g., pn diodes, pin diodes
H10D   8/01  B	1	1	5F087	H10D   8/01	1063	ѰΤΤ	for increasing breakdown voltage
H10D   8/01  S	1	0	5F087	H10D   8/01	1375	åȥХꥢɤ¤ˡħΤ	characterized by the manufacturing methods of Schottky barrier diodes
H10D   8/01  Z	1	0	5F087	H10D   8/01	0	¾Τ	Others
H10D   8/20  \	1	1	5F087	H10D   8/20	52	֥졼ɡ㡥Х󥷥ɡΣ	Breakdown diodes, e.g. avalanche diodes[2025.01]
H10D   8/20  P	1	0	5F087	H10D   8/20	128	ѥ롼Ű	punch-through type reference voltage diodes
H10D   8/20  Z	1	0	5F087	H10D   8/20	409	¾Τ	Others
H10D   8/25  \	2	2	5F087	H10D   8/25	1363	ĥʡɡΣ	Zener diodes[2025.01]
H10D   8/25  S	2	0	5F087	H10D   8/25	279	Τ	bidirectional
H10D   8/25  C	2	0	5F087	H10D   8/25	100	򤷤	compensating temperature
H10D   8/25  Z	2	0	5F087	H10D   8/25	3	¾Τ	Others
H10D   8/30  \	1	1	5F087	H10D   8/30	16	ܿɡΣ	Point-contact diodes[2025.01]
H10D   8/40  \	1	1	5F087	H10D   8/40	737	ȥ󥸥åȥɡ㡥ɣͣУԣԥɤޤϣԣңУԣԥɡΣ	Transit-time diodes, e.g. IMPATT or TRAPATT diodes[2025.01]
H10D   8/50  \	1	1	5F087	H10D   8/50	83	УɣΥɡΣ	PIN diodes[2025.01]
H10D   8/50  C	1	0	5F087	H10D   8/50	2462	¤ħΤ	characterized by the structures
H10D   8/50  D	1	1	5F087	H10D   8/50	2395	ѰΤΤ	for Increasing breakdown voltage
H10D   8/50  E	1	0	5F087	H10D   8/50	535	ȾƳΤñ뾽ꥳ󤫤ʤ	semiconductor bodies composed of non-single crystal silicon
H10D   8/50  F	1	0	5F087	H10D   8/50	2331	ȾƳΤꥳʳΤ	semiconductor bodies made of the materials other than silicon
H10D   8/50  G	1	1	5F087	H10D   8/50	156	ȾƳΤͭʪʤ	semiconductor bodies made of organic materials
H10D   8/50  H	1	0	5F087	H10D   8/50	405	إƥܹѤ	in which using heterojunctions were used
H10D   8/50  J	1	0	5F087	H10D   8/50	783	饤ե७顼˴ؤ	in relation to life time killers
H10D   8/50  K	1	0	5F087	H10D   8/50	1498	ʣɤȹ礻˴ؤ	in relation to the combination of multiple diodes
H10D   8/50  L	1	0	5F087	H10D   8/50	808	Ѳ˴ؤ	in relation to integration
H10D   8/50  Z	1	0	5F087	H10D   8/50	770	¾Τ	Others
H10D   8/60  \	1	1	5F087	H10D   8/60	6	åȥХꥢɡΣ	Schottky-barrier diodes[2025.01]
H10D   8/60  F	1	0	5F087	H10D   8/60	3006	ǻҹ¤	structures of elements
H10D   8/60  M	1	0	5F087	H10D   8/60	981	åȥŶˤκꤵƤ	in which the materials used for the electrodes for Schottky are limited
H10D   8/60  E	1	0	5F087	H10D   8/60	1395	ո̤δ	reducing surrounding effects
H10D   8/60  D	1	0	5F087	H10D   8/60	3272	ȾƳΤꥳʳΤ	semiconductor bodies made of the materials other than silicon
H10D   8/60  Z	1	0	5F087	H10D   8/60	65	¾Τ	Others
H10D   8/70  \	1	1	5F087	H10D   8/70	29	ȥ̥ͥɡΣ	Tunnel-effect diodes[2025.01]
H10D   8/70  F	1	0	5F087	H10D   8/70	167	ؤѤƤ	using insulation layers
H10D   8/70  S	1	0	5F087	H10D   8/70	242	Ķʻҹ¤ѤƤ	using superlattice structures
H10D   8/70  Z	1	0	5F087	H10D   8/70	273	¾Τ	Others
H10D   8/75  \	2	2	5F087	H10D   8/75	58	ȥ̣ͥУΥɡ㡥ɡΣ	Tunnel-effect PN diodes, e.g. Esaki diodes[2025.01]
H10D   8/80  \	1	1	5F087	H10D   8/80	46	УΣУΥɡ㡥å졼ɤޤϥ֥졼СɡΣ	PNPN diodes, e.g. Shockley diodes or break-over diodes[2025.01]
H10D  10/00  \	0	0	5F203	H10D  10/00	20146	Хݡȥ󥸥Σ£ʣԡϡΣ	Bipolar junction transistors [BJT][2025.01]
H10D  10/01  \	1	1	5F203	H10D  10/01	9058	¤ޤϽΣ	Manufacture or treatment[2025.01]
H10D  10/40  \	1	1	5F203	H10D  10/40	1	ķХݡȥ󥸥Σ	Vertical BJTs[2025.01]
H10D  10/40  S	1	0	5F203	H10D  10/40	2405	ե饤󷿥Хݡȥ󥸥㡥ӣӣԡӣţ£	self-aligned bipolar transistors, e.g., SST,SEBT
H10D  10/40  P	1	0	5F203	H10D  10/40	4834	ץ졼ʷХݡȥ󥸥	planar type bipolar transistors
H10D  10/40  Z	1	0	5F203	H10D  10/40	2	¾Τ	Others
H10D  10/60  \	1	1	5F203	H10D  10/60	2463	Хݡȥ󥸥Σ	Lateral BJTs[2025.01]
H10D  10/80  \	1	1	5F203	H10D  10/80	3424	إƥܹХݡȥ󥸥Σ	Heterojunction BJTs[2025.01]
H10D  12/00  \	0	0	5F111	H10D  12/00	19	ų̤ˤ椵Хݡ֡㡥沈ȥХݡȥ󥸥Σɣǣ£ԡϡΣ	Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT][2025.01]
H10D  12/00 101 \	1	1	5F111	H10D  12/00	12	ȾƳΰħΤ	characterized by semiconductor regions
H10D  12/00 101 A	1	0	5F111	H10D  12/00	599	ȥ󥸥ħΤ	characterized by transistor cells
H10D  12/00 101 B	1	1	5F111	H10D  12/00	369	ߥåΰ	emitter regions
H10D  12/00 101 C	1	1	5F111	H10D  12/00	700	١ΰ表ܥǥΰ	base regions;body regions
H10D  12/00 101 D	1	2	5F111	H10D  12/00	667	ǻ	high concentration parts;low resistance parts
H10D  12/00 101 E	1	2	5F111	H10D  12/00	232	ͥ	channel parts
H10D  12/00 101 F	1	1	5F111	H10D  12/00	682	Խʪΰʿ̷ޤ֥ѥħΤ	characterized by the planar shapes or the arrangement patterns of impurities ranges comprised of the cells
H10D  12/00 101 G	1	0	5F111	H10D  12/00	874	쥯ΰħΤ	characterized by collector regions
H10D  12/00 101 R	1	1	5F111	H10D  12/00	917	ɥեΰȥ쥯ŶˤȤʬŪû	partially short circuiting drift regions and collector electrodes
H10D  12/00 101 H	1	0	5F111	H10D  12/00	1771	ɥեΰħΤ	characterized by drift regions
H10D  12/00 101 J	1	1	5F111	H10D  12/00	11	Ķܹͭ	having super-junctions
H10D  12/00 101 K	1	1	5F111	H10D  12/00	3	ʣƣţΰͭ	having JFET regions
H10D  12/00 101 L	1	1	5F111	H10D  12/00	59	ɥեΰɽ̤ƱƳŷǻ٤ۤʤΰͭ	having the regions of different concentrations but the same conductivity type on the surface of a drift region
H10D  12/00 101 M	1	1	5F111	H10D  12/00	26	ɥեΰɽ̤¾Ƴŷΰͭ	having the regions of different conductivity types on the surface of a drift region
H10D  12/00 101 P	1	0	5F111	H10D  12/00	1485	ХåեؤħΤ	characterized by buffer layers
H10D  12/00 101 S	1	0	5F111	H10D  12/00	326	ꥢΰȴΤΰɲä	adding regions for carrier extraction
H10D  12/00 101 T	1	0	5F111	H10D  12/00	1879	ĤιħΤΡ㡥ʪȾƳΤѤΡ̤ħΤ	characterized by the constituent materials of substrates, e.g., using compound semiconductors, characterized by plane orientation
H10D  12/00 101 Z	1	0	5F111	H10D  12/00	550	¾Τ	Others
H10D  12/00 102 \	1	1	5F111	H10D  12/00	470	ŶˤħΤ	characterized by electrodes
H10D  12/00 102 G	1	0	5F111	H10D  12/00	794	ͣϣӥȡ㡥Ŷˡ졤ɹ¤ħΤ	characterized by MOS gates, e.g., the electrode, the insulation films or the shield structures
H10D  12/00 102 A	1	1	5F111	H10D  12/00	229	ŶˤηħΤ	characterized by the shapes of gate electrodes
H10D  12/00 102 B	1	1	5F111	H10D  12/00	287	ηħΤ	characterized by the shapes of gate insulation films
H10D  12/00 102 C	1	1	5F111	H10D  12/00	95	ȤӤƳΡ㡥ߡȡͭ	having conductors attached to the gates, e.g., dummy gates
H10D  12/00 102 S	1	0	5F111	H10D  12/00	251	ߥåŶˤħΤ	characterized by gate electrodes
H10D  12/00 102 D	1	1	5F111	H10D  12/00	626	ʣؤʤ	comprised of multiple layers
H10D  12/00 102 E	1	1	5F111	H10D  12/00	512	ħΤ	characterized by the shapes
H10D  12/00 102 F	1	2	5F111	H10D  12/00	437	󥿥ʿ̤Ǥʤ	having contact parts which are not planar
H10D  12/00 102 Z	1	0	5F111	H10D  12/00	0	¾Τ	Others
H10D  12/00 103 \	1	1	5F111	H10D  12/00	1716	åפμ뤤ϥåΤħΤ	characterized by the whole chip or peripheral parts around a chip
H10D  12/00 103 A	1	0	5F111	H10D  12/00	199	üΰѰ¤ħΤ	characterized by termination regions' structures which increase the breakdown voltage of semiconductors
H10D  12/00 103 B	1	1	5F111	H10D  12/00	590	ΰϤԽʪΰڤŶˤͭΡ㡥ɥ󥰵ڤӥեɥץ졼Ȥͭ	having impurity ranges or electrodes surrounding cell regions, e.g., having guard rings or field plates
H10D  12/00 103 C	1	1	5F111	H10D  12/00	757	ΰϤԽʪΰͭΡʣ¤ͥ	having impurity ranges surrounding cell regions (B takes precedence)
H10D  12/00 103 D	1	1	5F111	H10D  12/00	172	ΰϤŶˤͭΡʣ¤ͥ	Having electrodes surrounding cell regions (B takes precedence)
H10D  12/00 103 Q	1	0	5F111	H10D  12/00	1363	ѥåɤޤϼطħΤ	characterized by wring, pads and implementation relations
H10D  12/00 103 R	1	0	5F111	H10D  12/00	349	ʬΥΰħΤ	characterized by isolation regions
H10D  12/00 103 S	1	0	5F111	H10D  12/00	1922	ʣΥȥ󥸥ʿ̷ޤ֥ѥħΤ	characterized by the planar shapes or the arrangement patterns of multiple transistor cells
H10D  12/00 103 Z	1	0	5F111	H10D  12/00	5	¾Τ	Others
H10D  12/00 201 \	1	1	5F111	H10D  12/00	2	Ȥץ졼ʷǤʤ	having gates which are not planar types
H10D  12/00 201 A	1	0	5F111	H10D  12/00	3337	Ȥ¤˷Ρ㡥ֹ·ͣϣӡΣ֣ͣϣӡϡȥȷͣϣӡΣգͣϣӡ	having gates formed within grooves, e.g., V-groove type MOS[VMOS],trench gate type MOS[UMOS]
H10D  12/00 201 B	1	1	5F111	H10D  12/00	146	ͥΰ衤ߥå쥯ΰ¤˷	having channel regions, emitters and collector regions formed within grooves
H10D  12/00 201 C	1	0	5F111	H10D  12/00	738	Ȥ߷	with gates formed by burying them
H10D  12/00 201 D	1	0	5F111	H10D  12/00	36	ӣϣɤޤϣӣɣͣϣصѤѤ	using SOI or IMOX technologies
H10D  12/00 201 Z	1	0	5F111	H10D  12/00	22	¾Τ	Others
H10D  12/00 202 \	1	1	5F111	H10D  12/00	1	ưħΤ	characterized by operation
H10D  12/00 202 A	1	0	5F111	H10D  12/00	19	١ΰ˥Хä	giving biases to base regions
H10D  12/00 202 B	1	0	5F111	H10D  12/00	22	ꥢΰĤ	having minority carrier injection regions
H10D  12/00 202 C	1	0	5F111	H10D  12/00	56	ͣϣӷӣɣ	MOS type SIT
H10D  12/00 202 Z	1	0	5F111	H10D  12/00	152	¾Τ	Others
H10D  12/00 301 \	1	1	5F111	H10D  12/00	526	ɣǣ£	lateral IGBT
H10D  12/01  \	1	1	5F111	H10D  12/01	3	¤ޤϽΣ	Manufacture or treatment[2025.01]
H10D  12/01  A	1	0	5F111	H10D  12/01	1257	ԽʪΰηħΤ	characterized by the formation processes of impurity ranges
H10D  12/01  B	1	1	5F111	H10D  12/01	91	ե饤Ȼ	self-aligned diffusion
H10D  12/01  C	1	2	5F111	H10D  12/01	22	١ΰ֤	controlling the position of the midpoint parts of base wells
H10D  12/01  D	1	2	5F111	H10D  12/01	53	Ŷüΰ֤桤㡥¦ɻ	control of the position of the ends of gate electrode parts, e.g., oxidization on the sidewalls
H10D  12/01  E	1	0	5F111	H10D  12/01	490	ԽʪؤĹħΤ	characterized by the processes of impurity layer growth
H10D  12/01  F	1	0	5F111	H10D  12/01	969	ؤޤƳؤηħΤ	characterized by the formation processes of insulation layers or electricity conducting layers
H10D  12/01  G	1	0	5F111	H10D  12/01	643	å󥰤ħΤ	characterized by etching
H10D  12/01  H	1	0	5F111	H10D  12/01	778	饤եħΤ	characterized by lifetime control
H10D  12/01  J	1	0	5F111	H10D  12/01	172	ѥå١ħΤ	characterized by passivation
H10D  12/01  K	1	0	5F111	H10D  12/01	154	ϤŽ碌ħΤ	characterized by lamination of wafers
H10D  12/01  L	1	0	5F111	H10D  12/01	241	¬ޤϥߥ졼ħΤ	characterized by tests, measurements or simulation
H10D  12/01  Z	1	0	5F111	H10D  12/01	239	¾Τ	Others
H10D  18/00  \	0	0	5F005	H10D  18/00	337	ꥹΣ	Thyristors[2025.01]
H10D  18/00  A	0	0	5F005	H10D  18/00	406	ߥåû¤	emitter short-circuit structures
H10D  18/00  B	0	0	5F005	H10D  18/00	800	ɽ̹¤㡥ѥå١󡤥ɥ󥰡	surface structures, e.g., passivation, guard rings, grooves
H10D  18/00  V	0	1	5F005	H10D  18/00	841	̡㡥٥٥롤ͭ	having tilted surfaces, e.g., bevels
H10D  18/00  W	0	1	5F005	H10D  18/00	1209	ʿ̥ѥ㡥¿ߥåλŶ	planar patterns, e.g., multi-island emitters, comb tooth shaped electrodes
H10D  18/00  D	0	0	5F005	H10D  18/00	770	ԣޤϥȹ¤	contract ratio-to-transmittance[Ton]characteristics or gate structures
H10D  18/00  X	0	1	5F005	H10D  18/00	498	ȥȡڹ	trench gates;cut gates
H10D  18/00  Y	0	1	5F005	H10D  18/00	67	ξ̥	double-sided gates
H10D  18/00  E	0	0	5F005	H10D  18/00	889	ޤȯꥹ	light-sensitive or light emitting thyristors
H10D  18/00  F	0	0	5F005	H10D  18/00	1039	УΣУΰ	PNPN in general
H10D  18/00  G	0	0	5F005	H10D  18/00	799	ץ졼ʵѤޤϽѲ	planar technologies or integration
H10D  18/00  H	0	0	5F005	H10D  18/00	327	Ƴ̥ꥹ	reverse conducting thyristors
H10D  18/00  C	0	0	5F005	H10D  18/00	19	˻ߥꥹ	reverse blocking thyristors
H10D  18/00  J	0	0	5F005	H10D  18/00	830	ꥹŶ˹¤	thyristor electrode structures
H10D  18/00  L	0	0	5F005	H10D  18/00	312	ٻ	supports
H10D  18/00  M	0	0	5F005	H10D  18/00	647	ͶƳꥹ	static induction thyristors
H10D  18/00  P	0	0	5F005	H10D  18/00	247	ǻ	external elements
H10D  18/00  R	0	0	5F005	H10D  18/00	76	Ǯꥹ	heat-sensitive thyristors
H10D  18/00  S	0	0	5F005	H10D  18/00	30	ꥹ	presser-sensitive thyristors
H10D  18/00  T	0	0	5F005	H10D  18/00	9	ꥹ	magnetic sensitive thyristors
H10D  18/00  U	0	0	5F005	H10D  18/00	71	ꥹ	thyristors in general
H10D  18/00  Z	0	0	5F005	H10D  18/00	267	¾Τ	Others
H10D  18/01  \	1	1	5F005	H10D  18/01	0	¤ޤϽΣ	Manufacture or treatment[2025.01]
H10D  18/01  A	1	0	5F005	H10D  18/01	383	ꥹ¤ΤñʳħΤ	characterized by single-step processes for manufacturing thyristors
H10D  18/01  B	1	0	5F005	H10D  18/01	136	ꥹ¤Τ¿ʳħΤ	characterized by multi-step processes for manufacturing thyristors
H10D  18/01  C	1	1	5F005	H10D  18/01	26	ꥹΤΤ	for bidirectional thyristors
H10D  18/01  Z	1	0	5F005	H10D  18/01	0	¾Τ	Others
H10D  18/40  \	1	1	5F005	H10D  18/40	1	ų̤ˤ꥿󥪥󤹤ΡΣ	with turn-on by field effect[2025.01]
H10D  18/40  A	1	0	5F005	H10D  18/40	331	ͣϣӣƣţԤѤΡ㡥ͣϣӡã䡡ԣΣͣãԡ	using MOSFET, e.g., MOS Controlled Thyristor[MCT]
H10D  18/40  B	1	0	5F005	H10D  18/40	90	ƳĴ㡥ɣǣ£ԥ⡼ɡѤΡ㡥ţ򡡣ӣ䡡ԣΣţӣԡ	using conductivity modulation, e.g., IGBT mode, e.g., Emitter Switched Thyristor[EST]
H10D  18/40  C	1	0	5F005	H10D  18/40	77	ƳŷΰۤʤʣƣţԤѤΡ㡥£塡ң塡ԣΣ£ңԡ	using multiple different  FETs of conductivity types, e.g., Base Resistance Thyristor[BRT]
H10D  18/40  Z	1	0	5F005	H10D  18/40	2	¾Τ	Others
H10D  18/60  \	1	1	5F005	H10D  18/60	1364	ȥ󥪥եꥹΣ	Gate-turn-off devices[2025.01]
H10D  18/65  \	2	2	5F005	H10D  18/65	1	ų̤ˤ꥿󥪥դΡΣ	with turn-off by field effect[2025.01]
H10D  18/65  A	2	0	5F005	H10D  18/65	204	ͣϣӣƣţԤѤΡ㡥ͣϣӡã䡡ԣΣͣãԡ	using MOSFET, e.g., MOS Controlled Thyristor[MCT]
H10D  18/65  B	2	0	5F005	H10D  18/65	76	ƳĴ㡥ɣǣ£ԥ⡼ɡѤΡ㡥ţ򡡣ӣ䡡ԣΣţӣԡ	using conductivity modulation, e.g., IGBT mode, e.g., Emitter Switched Thyristor[EST]
H10D  18/65  C	2	0	5F005	H10D  18/65	93	ƳŷΰۤʤʣƣţԤѤΡ㡥£塡ң塡ԣΣ£ңԡ	using multiple different FETs of conductivity types, e.g., Base Resistance Thyristor[BRT]
H10D  18/65  Z	2	0	5F005	H10D  18/65	1	¾Τ	Others
H10D  18/80  \	1	1	5F005	H10D  18/80	572	ꥹ㡥ȥ饤åΣ	Bidirectional devices, e.g. triacs[2025.01]
H10D  30/00  \	0	0	5F140	H10D  30/00	0	ų̥ȥ󥸥Σƣţԡϡ沈ȥХݡȥ󥸥ȣģˡΣ	Field-effect transistors [FET] (insulated-gate bipolar transistors H10D 12/00)[2025.01]
H10D  30/01  \	1	1	5F123	H10D  30/01	0	¤ޤϽΣ	Manufacture or treatment[2025.01]
H10D  30/01 101 \	2	2	5F140	H10D  30/01	1	ȣģȣģޤȥ󥸥¤ޤϽ㡥沈ų̥ȥ󥸥ΣɣǣƣţԡϤ¤	manufacturing or treatment of transistors provided for in  H10D30/60~H10D30/65, e.g., manufacturing of insulated gate field effect transistor[IGFET]
H10D  30/01 101 F	2	0	5F140	H10D  30/01	729	ñΥץΤߤħΤ	characterized only by the single processes
H10D  30/01 101 P	2	0	5F140	H10D  30/01	4798	ͣϣӥץ㡥ɥ쥤ΰե饤󤪤Ŷ˷ΤΤ줫ĤΤߤħΤ	MOS processes, e.g., characterized only by either formation of source regions, drain regions or formation of self-align and electrodes
H10D  30/01 101 T	2	0	5F140	H10D  30/01	413	ޤ¬ħΤ	characterized by tests or measurements
H10D  30/01 101 Z	2	0	5F140	H10D  30/01	1982	¾Τ	Others
H10D  30/01 201 \	2	2	5F110	H10D  30/01	1	ȣģޤϣȣģޤȥ󥸥¤ޤϽ㡥ȥ󥸥ΣԣƣԡϤ¤	manufacturing or treatment of transistors provided for in H10D30/67 or H10D30/47,10, e.g., manufacturing of thin film transistors [TFT]
H10D  30/01 202 \	3	3	5F110	H10D  30/01	0	ɥ쥤¤ޤϽħΤ	characterized by the manufacturing or the treatment of sources, drains
H10D  30/01 202 J	3	0	5F110	H10D  30/01	400	ɥ쥤ηˡħΤ	characterized by methods of formation of sources, drains
H10D  30/01 202 K	3	1	5F110	H10D  30/01	2554	ɥ쥤ŶˤηˡħΤ	characterized by methods of formation of source electrodes, drain electrodes
H10D  30/01 202 L	3	1	5F110	H10D  30/01	1781	ɥ쥤ΰηˡħΤ	characterized by methods of formation of source regions, drain regions
H10D  30/01 202 M	3	2	5F110	H10D  30/01	516	ե饤	self-align
H10D  30/01 202 N	3	3	5F110	H10D  30/01	435	΢̤Ϫˤ	by exposure from the rear sides
H10D  30/01 202 Z	3	0	5F110	H10D  30/01	0	¾Τ	Others
H10D  30/01 203 \	3	3	5F110	H10D  30/01	3	Ȥ¤ޤϽħΤ	characterized by manufacturing or treatment of gates
H10D  30/01 203 V	3	0	5F110	H10D  30/01	2075	ηˡħΤ	characterized by methods of forming gate insulation films
H10D  30/01 203 W	3	1	5F110	H10D  30/01	390	۶˻ˡѤ	using methods for the production of anodic oxidation coatings
H10D  30/01 203 Z	3	0	5F110	H10D  30/01	2	¾Τ	Others
H10D  30/01 204 \	3	3	5F110	H10D  30/01	3504	ͥȾƳؤˡħΤ	characterized by the methods for the deposition of channel semiconductor layers
H10D  30/01 205 \	3	3	5F110	H10D  30/01	656	¬ޤϥߥ졼ħΤ	characterized by tests, measurements or simulation
H10D  30/01 206 \	3	3	5F110	H10D  30/01	10	¾ΥץħΤ	characterized by other processes
H10D  30/01 206 A	3	0	5F110	H10D  30/01	859	ʿó	flattening
H10D  30/01 206 B	3	0	5F110	H10D  30/01	495	Ϣ³	continuous formation
H10D  30/01 206 C	3	0	5F110	H10D  30/01	2833	ѥ˥	patterning
H10D  30/01 206 D	3	0	5F110	H10D  30/01	1727	Ž碌	lamination
H10D  30/01 206 E	3	0	5F110	H10D  30/01	583	󥰥󥰥ܥɤνüԤΡ㡥ǲ	passivating dangling bond defects, e.g., hydrogenation
H10D  30/01 206 F	3	0	5F110	H10D  30/01	1243	ˡ	annealing
H10D  30/01 206 G	3	1	5F110	H10D  30/01	5179	Ʒ뾽ñ뾽	recrystallisation;single crystallisation
H10D  30/01 206 Z	3	0	5F110	H10D  30/01	745	¾Τ	Others
H10D  30/01 301 \	2	2	5F111	H10D  30/01	7	ȣģޤȥ󥸥¤ޤϽ㡥ķģͣϣӡΣ֣ģͣϣӡų̥ȥ󥸥¤	manufacturing and treatment of transistors provided for in H10D30/66, e.g., manufacturing of vertical DMOS[VDMOS]field effect transistors
H10D  30/01 301 A	2	0	5F111	H10D  30/01	2607	ԽʪΰηħΤ	characterized by the processes for forming impurity ranges
H10D  30/01 301 B	2	1	5F111	H10D  30/01	340	ե饤Ȼ	self-aligned diffusion
H10D  30/01 301 C	2	2	5F111	H10D  30/01	96	١ΰ֤	controlling the positions of the midpoints of base wells
H10D  30/01 301 D	2	2	5F111	H10D  30/01	205	Ŷüΰ֤桤㡥¦ɻ	control of the position of the ends of gate electrode parts, e.g., oxidization of the sidewalls
H10D  30/01 301 E	2	0	5F111	H10D  30/01	1930	ԽʪؤĹħΤ	characterized by the processes of impurity layer growth
H10D  30/01 301 F	2	0	5F111	H10D  30/01	2802	ؤޤƳؤηħΤ	characterized by the steps for forming insulation layers and electricity conducting layers
H10D  30/01 301 G	2	0	5F111	H10D  30/01	1913	å󥰤ħΤ	characterized by etching
H10D  30/01 301 H	2	0	5F111	H10D  30/01	337	饤եħΤ	characterized by lifetime control
H10D  30/01 301 J	2	0	5F111	H10D  30/01	310	ѥå١ħΤ	characterized by passivation
H10D  30/01 301 K	2	0	5F111	H10D  30/01	233	ϤŽ碌ħΤ	characterized by lamination of wafers
H10D  30/01 301 L	2	0	5F111	H10D  30/01	290	¬ޤϥߥ졼ħΤ	characterized by inspections, measurements or simulation
H10D  30/01 301 Z	2	0	5F111	H10D  30/01	376	¾Τ	Others
H10D  30/01 401 \	2	2	5F102	H10D  30/01	10921	ȣģȣģޤϣȣģޤȥ󥸥¤ޤϽ㡥ήܹ祲Ŷˤͭų̥ȥ󥸥ޤϹŻҰư٥ȥ󥸥ΣȣţͣԡϤ¤	manufacturing and treatment of transistors provided for in H10D30/80~H10D30/87 or H10D30/47,201, e.g., manufacturing of field effect transistors [FET]or high electron mobility transistors [HEMT]having gate electrodes with rectifying junctions
H10D  30/01 501 \	2	2	5F101	H10D  30/01	12338	ȣģȣģޤȥ󥸥¤ޤϽ㡥եƥ󥰥ȤޤŲ٥ȥåԥ󥰥Τͭ沈ų̥ȥ󥸥¤	manufacturing and treatment of transistors provided for in H10D30/68~H10D30/69, e.g., manufacturing of insulated gate field effect transistors having floating gates or charge trapping gate insulators
H10D  30/40  \	1	1	5F123	H10D  30/40	279	ޤϣꥢͥͭų̥ȥ󥸥Σ	FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels[2025.01]
H10D  30/43  \	2	2	5F123	H10D  30/43	382	ꥢͥĤΡ㡥̻Һų̥ȥ󥸥ޤϣ̻Ĥͥͭȥ󥸥Σ	having one-dimensional [1D] charge carrier gas channels, e.g. quantum wire FETs or transistors having 1D quantum-confined channels[2025.01]
H10D  30/47  \	2	2	5F123	H10D  30/47	133	ꥢͥĤΡ㡥ʥΥܥų̥ȥ󥸥ޤϹŻҰư٥ȥ󥸥ΣȣţͣԡϡΣ	having two-dimensional [2D] charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT][2025.01]
H10D  30/47 101 \	3	3	5F110	H10D  30/47	1632	ʥΥܥ㡥ʥΥܥ󡤤Ѥȥ󥸥	transistors using nano-carbon, e.g., nano-ribbons
H10D  30/47 201 \	3	3	5F102	H10D  30/47	8689	ŻҰư٥ȥ󥸥Σȣţͣԡ	high electron mobility transistors [HEMT]
H10D  30/60  \	1	1	5F140	H10D  30/60	11811	沈ų̥ȥ󥸥ΣɣǣƣţԡϡʣȣģͥˡΣ	Insulated-gate field-effect transistors [IGFET] (H10D 30/40 takes precedence)[2025.01]
H10D  30/60  B	1	0	5F140	H10D  30/60	3237	ʪȾƳΤѤ	using compound semiconductors
H10D  30/60  C	1	0	5F140	H10D  30/60	1187	ͣϣӣɣäѤ	used for MOSIC
H10D  30/60  E	1	0	5F140	H10D  30/60	88	ϩΤߤħΤ	characterized only by the structures of circuits
H10D  30/60  G	1	0	5F140	H10D  30/60	7864	Ŷ˹¤ΤߤħΤ	characterized only by the structures of gate electrodes
H10D  30/60  H	1	0	5F140	H10D  30/60	1876	ͥ빽¤ΤߤħΤ	characterized only by channel structures
H10D  30/60  J	1	0	5F140	H10D  30/60	991	ȤưħΤ	characterized specially by operation
H10D  30/60  K	1	0	5F140	H10D  30/60	1823	ݸ	protective devices
H10D  30/60  L	1	0	5F140	H10D  30/60	2516	̣ģ	LDD
H10D  30/60  M	1	0	5F140	H10D  30/60	303	꡼ѤΡ㡥ԣ򡥣ģңͥ	used for memories, e.g., 1Tr.DRAM cells
H10D  30/60  N	1	0	5F140	H10D  30/60	724	ѥå١¤ΤߤħΤ	characterized only by the structure of passivation
H10D  30/60  Q	1	0	5F140	H10D  30/60	221	뾽̤ΤߤħΤ	characterized only by the selection of crystal orientation
H10D  30/60  R	1	0	5F140	H10D  30/60	1605	ʬΥΰΤߤħΤ	characterized only by isolation regions
H10D  30/60  S	1	0	5F140	H10D  30/60	3477	ɥ쥤ΰΤߤħΤ	characterized only by source regions, drain regions
H10D  30/60  U	1	0	5F140	H10D  30/60	289	ɣӣƣţ	ISFET
H10D  30/60  V	1	0	5F140	H10D  30/60	1192	¤ۤꥲȤĤ	having trenching gates
H10D  30/60  W	1	0	5F140	H10D  30/60	841	Ѱή㡥	Increasing the breakdown voltage, increases in the current, e.g., parallelizing
H10D  30/60  X	1	0	5F140	H10D  30/60	3949	¾Σͣϣӹ¤	other MOSstructures
H10D  30/60  Z	1	0	5F140	H10D  30/60	1077	¾㡥¤ӥץħΤ	others, e.g., characterized by both the structures and the processes
H10D  30/62  \	2	2	5F140	H10D  30/62	1403	եų̥ȥ󥸥ΣƣƣţԡϡΣ	Fin field-effect transistors [FinFET][2025.01]
H10D  30/63  \	2	2	5F140	H10D  30/63	1164	ķ沈ų̥ȥ󥸥ʣȣģͥˡΣ	Vertical IGFETs (H10D 30/66 takes precedence)[2025.01]
H10D  30/64  \	2	2	5F140	H10D  30/64	3	ųȻ°ʪΣģͣϣӡų̥ȥ󥸥Σ	Double-diffused metal-oxide semiconductor [DMOS] FETs[2025.01]
H10D  30/65  \	3	3	5F140	H10D  30/65	1455	ģͣϣӡΣ̣ģͣϣӡų̥ȥ󥸥Σ	Lateral DMOS [LDMOS] FETs[2025.01]
H10D  30/66  \	3	3	5F111	H10D  30/66	35	ķģͣϣӡΣ֣ģͣϣӡų̥ȥ󥸥Σ	Vertical DMOS [VDMOS] FETs[2025.01]
H10D  30/66 101 \	4	4	5F111	H10D  30/66	7	ȾƳΰħΤ	characterized by semiconductor regions
H10D  30/66 101 A	4	0	5F111	H10D  30/66	158	ȥ󥸥ħΤ	characterized by transistor cells
H10D  30/66 101 B	4	1	5F111	H10D  30/66	918	ΰ	source regions
H10D  30/66 101 C	4	1	5F111	H10D  30/66	1380	١ΰ表ܥǥΰ	base regions; body regions
H10D  30/66 101 D	4	2	5F111	H10D  30/66	1583	ǻ	high concentration parts; low density parts
H10D  30/66 101 E	4	2	5F111	H10D  30/66	986	ͥ	channel parts
H10D  30/66 101 F	4	1	5F111	H10D  30/66	2041	Խʪΰʿ̷ޤ֥ѥħΤ	characterized by the planar shapes or the arrangement patterns of impurity ranges comprising the cells
H10D  30/66 101 G	4	0	5F111	H10D  30/66	751	ɥ쥤ΰħΤ	characterized by drain regions
H10D  30/66 101 H	4	0	5F111	H10D  30/66	4142	ɥեΰħΤ	characterized by drift regions
H10D  30/66 101 J	4	1	5F111	H10D  30/66	50	Ķܹͭ	having super-junctions
H10D  30/66 101 K	4	1	5F111	H10D  30/66	16	ʣƣţΰͭ	having JFET regions
H10D  30/66 101 L	4	1	5F111	H10D  30/66	81	ɥեΰɽ̤ƱƳŷǻ٤ۤʤΰͭ	having the regions of different concentrations but of the same conductivity type on the surface of a drift region
H10D  30/66 101 M	4	1	5F111	H10D  30/66	88	ɥեΰɽ̤¾Ƴŷΰͭ	having the regions of different conductivity types on the surface of a drift region
H10D  30/66 101 T	4	0	5F111	H10D  30/66	6277	ĤιħΤΡ㡥ʪȾƳΤѤΡ̤ħΤ	characterized by the constituent materials of substrates, e.g., using compound semiconductors, characterized by plane orientation
H10D  30/66 101 Z	4	0	5F111	H10D  30/66	71	¾Τ	Others
H10D  30/66 102 \	4	4	5F111	H10D  30/66	830	ŶˤħΤ	characterized by electrodes
H10D  30/66 102 G	4	0	5F111	H10D  30/66	1936	ͣϣӥȡ㡥Ŷˡ졤ɹ¤ħΤ	characterized by MOS gates, e.g., the electrodes, insulation films, the shield structures
H10D  30/66 102 A	4	1	5F111	H10D  30/66	542	ŶˤηħΤ	characterized by the shapes of gate electrodes
H10D  30/66 102 B	4	1	5F111	H10D  30/66	999	ηħΤ	characterized by the shapes of gate insulating films
H10D  30/66 102 C	4	1	5F111	H10D  30/66	370	ȤӤƳΡ㡥ߡȡͭ	having electricity conducting bodies attached to the gates, e.g., dummy gates
H10D  30/66 102 S	4	0	5F111	H10D  30/66	591	ŶˤħΤ	characterized by source electrodes
H10D  30/66 102 D	4	1	5F111	H10D  30/66	1571	ʣؤʤ	comprised of multiple layers
H10D  30/66 102 E	4	1	5F111	H10D  30/66	884	ħΤ	characterized by the shapes
H10D  30/66 102 F	4	2	5F111	H10D  30/66	1145	󥿥ʿ̤Ǥʤ	having contact parts which are not planar
H10D  30/66 102 Z	4	0	5F111	H10D  30/66	4	¾Τ	Others
H10D  30/66 103 \	4	4	5F111	H10D  30/66	1661	åפμ뤤ϥåΤħΤ	characterized by areas surrounding a chip or a chip as a whole
H10D  30/66 103 A	4	0	5F111	H10D  30/66	422	üΰѰ¤ħΤ	characterized by termination regions' structures which increase the breakdown voltage of semiconductors
H10D  30/66 103 B	4	1	5F111	H10D  30/66	654	ΰϤԽʪΰڤŶˤͭΡ㡥ɥ󥰵ڤӥեɥץ졼Ȥͭ	having impurity ranges or electrodes surrounding cell regions, e.g., having guard rings and field plates
H10D  30/66 103 C	4	1	5F111	H10D  30/66	1322	ΰϤԽʪΰͭΡʣ¤ͥ	having impurity ranges surrounding cell regions (B takes precedence)
H10D  30/66 103 D	4	1	5F111	H10D  30/66	389	ΰϤŶˤͭΡʣ¤ͥ	having electrodes surrounding cell regions (B takes precedence)
H10D  30/66 103 Q	4	0	5F111	H10D  30/66	2040	ѥåɤޤϼطħΤ	Characterized by wring, pads and implementation relations
H10D  30/66 103 R	4	0	5F111	H10D  30/66	438	ʬΥΰħΤ	characterized by isolation regions
H10D  30/66 103 S	4	0	5F111	H10D  30/66	2213	ʣΥȥ󥸥ʿ̷ޤ֥ѥħΤ	Characterized by the planar shapes or the arrangement patterns of multiple transistor cells
H10D  30/66 103 Z	4	0	5F111	H10D  30/66	7	¾Τ	Others
H10D  30/66 201 \	4	4	5F111	H10D  30/66	7	Ȥץ졼ʷǤʤ	having gates which are not planar types
H10D  30/66 201 A	4	0	5F111	H10D  30/66	5628	Ȥ¤˷Ρ㡥ֹ·ͣϣӡΣ֣ͣϣӡϡȥȷͣϣӡΣգͣϣӡ	in which gates are formed within grooves, e.g., V-groove type MOS[VMOS],trench gate type MOS[UMOS]
H10D  30/66 201 B	4	1	5F111	H10D  30/66	558	ͥΰ衤ɥ쥤ΰ¤˷	in which channel regions, source regions, drain regions are formed within grooves
H10D  30/66 201 C	4	0	5F111	H10D  30/66	1548	Ȥ߷	with gates formed by burying them
H10D  30/66 201 D	4	0	5F111	H10D  30/66	154	ӣϣɤޤϣӣɣͣϣصѤѤ	using SOI or IMOX technologies
H10D  30/66 201 Z	4	0	5F111	H10D  30/66	98	¾Τ	Others
H10D  30/66 202 \	4	4	5F111	H10D  30/66	3	ưħΤ	characterized by operation
H10D  30/66 202 A	4	0	5F111	H10D  30/66	31	١ΰ˥Хä	giving biases to base regions
H10D  30/66 202 B	4	0	5F111	H10D  30/66	38	ꥢΰĤ	having minority carrier injection regions
H10D  30/66 202 C	4	0	5F111	H10D  30/66	183	ͣϣӷӣɣ	MOS type SIT
H10D  30/66 202 Z	4	0	5F111	H10D  30/66	252	¾Τ	Others
H10D  30/67  \	2	2	5F110	H10D  30/67	42	ȥ󥸥ΣԣƣԡϡΣ	Thin-film transistors [TFT][2025.01]
H10D  30/67 101 \	3	3	5F110	H10D  30/67	8	ɥ쥤ħΤ	characterized by sources, drains
H10D  30/67 101 A	3	0	5F110	H10D  30/67	1797	̣ģġ㡥¤ˡħΤ	characterized by LDD,e.g., the structures and the manufacturing methods
H10D  30/67 101 S	3	0	5F110	H10D  30/67	1708	ɥ쥤ΰ衤Ŷˤι¤ħΤ	characterized by the structures of source regions, drain regions and electrodes
H10D  30/67 101 T	3	1	5F110	H10D  30/67	2576	ħΤ	characterized by the shapes
H10D  30/67 101 U	3	1	5F110	H10D  30/67	2230	ʣ	multiple layers
H10D  30/67 101 V	3	1	5F110	H10D  30/67	4207	ԽʪǻħΤ	characterized by materials, the concentrations of impurities
H10D  30/67 101 Z	3	0	5F110	H10D  30/67	35	¾Τ	Others
H10D  30/67 102 \	3	3	5F110	H10D  30/67	6	ȤħΤ	characterized by the gates
H10D  30/67 102 A	3	0	5F110	H10D  30/67	703	եåȥȡ㡥¤ˡħΤ	characterized by offset gates, e.g., the structures, the manufacturing methods
H10D  30/67 102 J	3	0	5F110	H10D  30/67	1883	ŶˤħΤ	characterized by gate electrodes
H10D  30/67 102 K	3	1	5F110	H10D  30/67	2086	ħΤ	characterized by the shapes
H10D  30/67 102 L	3	1	5F110	H10D  30/67	1356	ʣ	multiple layers
H10D  30/67 102 M	3	1	5F110	H10D  30/67	1851	ԽʪǻħΤ	characterized by the materials, the concentrations of impurities
H10D  30/67 102 N	3	1	5F110	H10D  30/67	2663	Ŷˤʣͭ	having multiple gate electrodes
H10D  30/67 102 S	3	0	5F110	H10D  30/67	1140	ħΤ	characterized by gate insulating films
H10D  30/67 102 T	3	1	5F110	H10D  30/67	2963	ħΤ	characterized by the materials
H10D  30/67 102 U	3	1	5F110	H10D  30/67	2100	ʣ	multiple layers
H10D  30/67 102 Z	3	0	5F110	H10D  30/67	45	¾Τ	Others
H10D  30/67 103 \	3	3	5F110	H10D  30/67	23	ͥȾƳؤħΤ	characterized by channel semiconductor layers
H10D  30/67 103 B	3	0	5F110	H10D  30/67	18334	ħΤ	characterized by the materials
H10D  30/67 103 C	3	0	5F110	H10D  30/67	3159	ħΤ	characterized by the shapes
H10D  30/67 103 D	3	1	5F110	H10D  30/67	543	첽	thinning of film thickness
H10D  30/67 103 E	3	0	5F110	H10D  30/67	2502	ʣ	multiple layers
H10D  30/67 103 F	3	0	5F110	H10D  30/67	1432	ԽʪԽʪǻħΤ	characterized by impurities and the concentrations of impurities
H10D  30/67 103 G	3	1	5F110	H10D  30/67	694	ꥢˤʤʤԽʪޤ	including impurities which do not act as carriers
H10D  30/67 103 Z	3	0	5F110	H10D  30/67	1690	¾Τ	Others
H10D  30/67 104 \	3	3	5F110	H10D  30/67	27	ѥå١ħΤ	characterized by passivation
H10D  30/67 104 A	3	0	5F110	H10D  30/67	4810	졤㡥¤ˡħΤ	characterized by insulation films, e.g., the structures, the manufacturing methods, the materials
H10D  30/67 104 B	3	0	5F110	H10D  30/67	1436	׸졤㡥¤ˡħΤ	characterized by light shielding films, e.g., the structures, the manufacturing methods, the materials
H10D  30/67 104 Z	3	0	5F110	H10D  30/67	15	¾Τ	Others
H10D  30/67 201 \	3	3	5F110	H10D  30/67	844	뾽̤ħΤ	characterized by the selection of crystal orientation
H10D  30/67 202 \	3	3	5F110	H10D  30/67	1444	ʬΥΰħΤ	characterized by isolation regions
H10D  30/67 203 \	3	3	5F110	H10D  30/67	1141	äưħΤ	characterized by operation
H10D  30/67 204 \	3	3	5F110	H10D  30/67	29	ݸ֡ݸϩ	protective devices:protection circuits
H10D  30/67 204 A	3	0	5F110	H10D  30/67	810	˲ɻߡ㡥ӥ󥰻˲ɻ	electrostatic breakdown prevention, e.g., electric breakdown prevention when ion implantation, labyrinth processes are performed
H10D  30/67 204 Z	3	0	5F110	H10D  30/67	209	¾Τ	Others
H10D  30/67 205 \	3	3	5F110	H10D  30/67	140	ɣӣƣţ	ISFET
H10D  30/67 206 \	3	3	5F110	H10D  30/67	7	¾ι¤	Other structures
H10D  30/67 206 A	3	0	5F110	H10D  30/67	949	ķ¤	vertical structures
H10D  30/67 206 B	3	0	5F110	H10D  30/67	676	ɻ	kink suppression
H10D  30/67 206 C	3	0	5F110	H10D  30/67	4261	ɽؤޤĤħΤ	characterized by the substrates including surface layers
H10D  30/67 206 D	3	1	5F110	H10D  30/67	524	ĤӣϣӤʤ	substrates composed of SOS
H10D  30/67 206 Z	3	0	5F110	H10D  30/67	533	¾Τ	Others
H10D  30/68  \	2	2	5F101	H10D  30/68	14844	եƥ󥰥Ȥͭ沈ų̥ȥ󥸥Σ	Floating-gate IGFETs[2025.01]
H10D  30/69  \	2	2	5F101	H10D  30/69	10371	Ų٥ȥåԥ󥰥Τͭ沈ų̥ȥ󥸥㡥ͣΣϣӥȥ󥸥Σ	IGFETs having charge trapping gate insulators, e.g. MNOS transistors[2025.01]
H10D  30/80  \	1	1	5F102	H10D  30/80	3027	ήܹ祲Ŷˤͭų̥ȥ󥸥ʣȣģͥˡΣ	FETs having rectifying junction gate electrodes (H10D 30/40 takes precedence)[2025.01]
H10D  30/80  A	1	0	5F102	H10D  30/80	708	ǻҤμ	kinds of elements
H10D  30/80  S	1	1	5F102	H10D  30/80	119	ӣɣ	lateral SIT
H10D  30/80  V	1	1	5F102	H10D  30/80	2402	ķƣţ	vertical FET
H10D  30/80  W	1	0	5F102	H10D  30/80	506	ģ졡ǣ幽¤ͭ	having Dual Gate structures
H10D  30/80  P	1	0	5F102	H10D  30/80	393	ݸǽͭ	having protective functions
H10D  30/80  Z	1	0	5F102	H10D  30/80	233	¾Τ	Others
H10D  30/83  \	2	2	5F102	H10D  30/83	2655	Уܹ祲Ŷˤͭų̥ȥ󥸥Σ	FETs having PN junction gate electrodes[2025.01]
H10D  30/87  \	2	2	5F102	H10D  30/87	0	åȥŶˤͭų̥ȥ󥸥㡥°ȾƳų̥ȥ󥸥ΣͣţӣƣţԡϡΣ	FETs having Schottky gate electrodes, e.g. metal-semiconductor FETs [MESFET][2025.01]
H10D  30/87  B	2	0	5F102	H10D  30/87	3601	ͣţӷƣţ	MES type FET
H10D  30/87  F	2	1	5F102	H10D  30/87	4471	Ŷˤħͭ	characterized by electrodes
H10D  30/87  S	2	2	5F102	H10D  30/87	6	ߥåŶˡ㡥Ŷˡɥ쥤Ŷ	ohmic electrodes, e.g., source electrodes, drain electrodes
H10D  30/87  K	2	2	5F102	H10D  30/87	123	Ф	using oblique deposition
H10D  30/87  L	2	2	5F102	H10D  30/87	867	Ŷʿ̹¤	planar construction of electrodes
H10D  30/87  M	2	2	5F102	H10D  30/87	480	Ŷ˺	materials for gate electrodes
H10D  30/87  U	2	2	5F102	H10D  30/87	582	΢Ŷ˼Ф	removal of backside electrodes
H10D  30/87  Q	2	1	5F102	H10D  30/87	550	ɽ̹ؤͭ	having high resistance layers on the surfaces
H10D  30/87  R	2	1	5F102	H10D  30/87	332	ϩԲϩβ	integrating matching circuits with feedback circuits
H10D  30/87  G	2	1	5F102	H10D  30/87	403		implementation
H10D  30/87  E	2	1	5F102	H10D  30/87	2064	Ѳ	integration
H10D  30/87  Z	2	0	5F102	H10D  30/87	1	¾Τ	Others
H10D  44/00  \	0	0	4M118	H10D  44/00	25	Ųž֡Σ	Charge transfer devices[2025.01]
H10D  44/00  D	0	0	4M118	H10D  44/00	105	¤	structures
H10D  44/00  A	0	1	4M118	H10D  44/00	1627	ž	transfer sections
H10D  44/00  B	0	2	4M118	H10D  44/00	264	ưϩ	drive circuits
H10D  44/00  C	0	1	4M118	H10D  44/00	1104		input parts;output parts;reproduction parts
H10D  44/00  E	0	0	4M118	H10D  44/00	71	ǻ	applied elements
H10D  44/00  F	0	1	4M118	H10D  44/00	82	եȥ쥸ٱ	shift registers;delay lines
H10D  44/00  G	0	1	4M118	H10D  44/00	186		memory devices
H10D  44/00  H	0	1	4M118	H10D  44/00	108	ե륿	filters
H10D  44/00  J	0	1	4M118	H10D  44/00	134	ǻ	image sensors
H10D  44/00  K	0	0	4M118	H10D  44/00	15	Ķȶưˤ	by ultrasonic wave drives
H10D  44/00  L	0	0	4M118	H10D  44/00	103	Хåȡ֥ꥲǻ	bucket brigade elements
H10D  44/00  Z	0	0	4M118	H10D  44/00	19	¾Τ	Others
H10D  44/01  \	1	1	4M118	H10D  44/01	864	¤ޤϽΣ	Manufacture or treatment[2025.01]
H10D  44/40  \	1	1	4M118	H10D  44/40	0	Ųٷ֡ΣããġϡΣ	Charge-coupled devices [CCD][2025.01]
H10D  44/45  \	2	2	4M118	H10D  44/45	0	沈Ŷˤˤų̤ĤΡΣ	having field effect produced by insulated gate electrodes[2025.01]
H10D  48/00  \	0	0	5F123	H10D  48/00	105	롼ףȣģȣģޤʤġ֡Σ	Individual devices not covered by groups H10D 1/00-H10D 44/00[2025.01]
H10D  48/00 101 \	1	1	5F123	H10D  48/00	621	ǥХߥ졼	device simulation
H10D  48/01  \	1	1	5F123	H10D  48/01	0	¤ޤϽΣ	Manufacture or treatment[2025.01]
H10D  48/04  \	2	2	5F123	H10D  48/04	83	礷Ƥʤ֤Υޤϥƥ뤫ʤΤ֤ͭΤΡΣ	of devices having bodies comprising selenium or tellurium in uncombined form[2025.01]
H10D  48/042  \	3	3	5F123	H10D  48/042	18	ĤνΣ	Preparation of foundation plates[2025.01]
H10D  48/043  \	3	3	5F123	H10D  48/043	3	ޤϥƥĤؤŬѡޤ³ƤηΣ	Preliminary treatment of the selenium or tellurium, its application to foundation plates or the subsequent treatment of the combination[2025.01]
H10D  48/044  \	4	4	5F123	H10D  48/044	0	ޤϥƥƳž֤ؤѴΣ	Conversion of the selenium or tellurium to the conductive state[2025.01]
H10D  48/045  \	4	4	5F123	H10D  48/045	2	ƳˤΥޤϥƥؤɽ̽Σ	Treatment of the surface of the selenium or tellurium layer after having been made conductive[2025.01]
H10D  48/046  \	4	4	5F123	H10D  48/046	2	ʬΥؤηΣ	Provision of discrete insulating layers[2025.01]
H10D  48/047  \	3	3	5F123	H10D  48/047	4	ĤŬѤΥޤϥƥϪ̤ؤŶˤηΣ	Application of an electrode to the exposed surface of the selenium or tellurium after the selenium or tellurium has been applied to foundation plates[2025.01]
H10D  48/048  \	3	3	5F123	H10D  48/048	3	֤ν㡥ɷΤΥ쥯ȥեߥ󥰤ˤΡΣ	Treatment of the complete device, e.g. by electroforming to form a barrier[2025.01]
H10D  48/049  \	4	4	5F123	H10D  48/049	3	󥰡Σ	Ageing[2025.01]
H10D  48/07  \	2	2	5F123	H10D  48/07	2	ƼΣãϡϤޤϥ襦ƼΣãϤʤΤ֤ͭΤΡΣ	of devices having bodies comprising cuprous oxide [Cu2O] or cuprous iodide [CuI][2025.01]
H10D  48/30  \	1	1	5F123	H10D  48/30	1211	ήޤŰˤ椵֡Σ	Devices controlled by electric currents or voltages[2025.01]
H10D  48/30  S	1	0	5F123	H10D  48/30	396	ñŻҥȥͥ󥰡㡥֥åɸ̡Ѥ	using single electron tunneling, e.g., coulomb blockade effects
H10D  48/30  U	1	1	5F123	H10D  48/30	101	ѲϩħΤ	characterized by integration, circuit structures
H10D  48/30  T	1	0	5F123	H10D  48/30	383	ȥ̤ͥѤΡʣӤͥ	using tunneling effects (S takes precedence)
H10D  48/30  E	1	0	5F123	H10D  48/30	106	Żǻҡųǻҡ㡥䱢ˤѤǻ	electron emission devices, electric field emission elements, e.g., emission elements using cold cathode fluorescent
H10D  48/30  C	1	0	5F123	H10D  48/30	85	ʤħΤ	characterized by control methods
H10D  48/30  L	1	1	5F123	H10D  48/30	53	Ѥ	using light
H10D  48/30  M	1	1	5F123	H10D  48/30	69	Ѥ	using magnetic fields
H10D  48/30  Z	1	0	5F123	H10D  48/30	356	¾Τ	Others
H10D  48/32  \	2	2	5F203	H10D  48/32	1026	ήޤϥåήήʤŶˤͿήޤṲ̋Τߤˤ椵֡Σ	Devices controlled by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched[2025.01]
H10D  48/34  \	3	3	5F203	H10D  48/34	185	Хݡ֡Σ	Bipolar devices[2025.01]
H10D  48/36  \	3	3	5F140	H10D  48/36	527	˥ݡ֡Σ	Unipolar devices[2025.01]
H10D  48/38  \	2	2	5F087	H10D  48/38	59	ήȯޤϥåήήİʾŶˤͿήޤṲ̋ѲΤߤˤ椵֡Σ	Devices controlled only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched[2025.01]
H10D  48/38  A	2	0	5F087	H10D  48/38	49	ñ뾽ѤƤ	using non-single crystal
H10D  48/38  F	2	0	5F087	H10D  48/38	72	ؤѤƤ	using insulation layers
H10D  48/38  S	2	0	5F087	H10D  48/38	47	Ķʻҹ¤ѤƤ	using superlattice structures
H10D  48/38  Z	2	0	5F087	H10D  48/38	320	¾Τ	Others
H10D  48/40  \	1	1	5F092	H10D  48/40	29	ˤ椵֡Σ	Devices controlled by magnetic fields[2025.01]
H10D  48/40  D	1	0	5F092	H10D  48/40	95	ӣͣ	SMD
H10D  48/40  T	1	0	5F092	H10D  48/40	61	ӣͣ	SMT
H10D  48/40  Z	1	0	5F092	H10D  48/40	2938	¾Τ	Others
H10D  48/50  \	1	1	4M112	H10D  48/50	89	Ūϡ㡥ϡˤ椵֡Σ	Devices controlled by mechanical forces, e.g. pressure[2025.01]
H10D  48/50  A	1	0	4M112	H10D  48/50	3269	ŪϡŵѴ	conversion of mechanical force into electricity
H10D  48/50  B	1	0	4M112	H10D  48/50	3147	ꥳե	silicon diaphragms
H10D  48/50  C	1	0	4M112	H10D  48/50	196	ƣţ	pressure sensitive FET
H10D  48/50  D	1	0	4M112	H10D  48/50	95		pressure sensitive diodes
H10D  48/50  E	1	0	4M112	H10D  48/50	74	Ӥ췿ꥹ	constricted, pressure sensitive thyristors
H10D  48/50  F	1	0	4M112	H10D  48/50	132	ȥ󥸥	pressure sensitive transistors
H10D  48/50  G	1	0	4M112	H10D  48/50	124	ð	pressurizing mechanisms
H10D  48/50  H	1	0	4M112	H10D  48/50	86	ӣϣ̤ͭ	SnO2;having deep levels
H10D  48/50  J	1	0	4M112	H10D  48/50	78	ĶѴ	conversion of ultrasonic waves
H10D  48/50  Z	1	0	4M112	H10D  48/50	4640	¾Τ	Others
H10D  62/00  \	0	0	5F121	H10D  62/00	31	Ű̾ɤ֤ͭȾƳΡޤϤΰΣ	Semiconductor bodies, or regions thereof, of devices having potential barriers[2025.01]
H10D  62/10  \	1	1	5F121	H10D  62/10	1533	ȾƳΤΰηŪ礭ޤ֡ȾƳΤηΣ	Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies[2025.01]
H10D  62/10 101 \	2	2	5F139	H10D  62/10	3	Ѱ¤	pressure proof structures
H10D  62/10 101 M	2	0	5F139	H10D  62/10	963	¤ޤϷ̡㡥᥵٥٥롤	forming grooves or tilted surfaces,e.g., mesa, bevels
H10D  62/10 101 F	2	0	5F139	H10D  62/10	2127	եɥץ졼ȤѤ	using field plates
H10D  62/10 101 S	2	0	5F139	H10D  62/10	138	Ⱦ졤Ѥ	using semi-insulating films, high resistance films
H10D  62/10 101 D	2	0	5F139	H10D  62/10	1578	ȾƳΰħΤΡ㡥Խʪǻ١ˡ֡ħΤΡʣҤͥ	characterized by semiconductor regions, e.g., characterized by concentrations, shapes, sizes, arrangements of impurities (R takes precedence)
H10D  62/10 101 G	2	1	5F139	H10D  62/10	2553	ɥ󥰡ų¥󥰤Ѥ	using guard rings, electric field limiting rings
H10D  62/10 101 R	2	0	5F139	H10D  62/10	263	̡ʿζΨ椹	limiting curvature, such as the curvature of a section or a plane
H10D  62/10 101 V	2	0	5F139	H10D  62/10	3300	ķǻѤΤ	for vertical devices
H10D  62/10 101 Z	2	0	5F139	H10D  62/10	91	¾Τ	Others
H10D  62/10 201 \	2	2	5F121	H10D  62/10	2	ü칽¤	special structures
H10D  62/10 201 N	2	0	5F121	H10D  62/10	1541	ʥι¤Ρ㡥ҥ٥롤ʬҥ٥ˤ	by manipulation of nanostructures, e.g., atom-level, molecular-level
H10D  62/10 201 B	2	0	5F121	H10D  62/10	94	Ωηǻҡ㡥ȾƳ	three-dimensional elements, e.g., spherical semiconductors
H10D  62/10 201 Z	2	0	5F121	H10D  62/10	204	¾Τ	Others
H10D  62/13  \	2	2	5F121	H10D  62/13	408	ήޤϥåήήŶˤ³ƤȾƳΰ衤㡥ޤϥɥ쥤ΰΣ	Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions[2025.01]
H10D  62/17  \	2	2	5F121	H10D  62/17	34	ήޤϥåήήʤŶˤ³ƤȾƳΰ衤㡥ͥΰΣ	Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions[2025.01]
H10D  62/40  \	1	1	5F121	H10D  62/40	237	뾽¤Σ	Crystalline structures[2025.01]
H10D  62/50  \	1	1	5F121	H10D  62/50	16	ʪŪԴΣ	Physical imperfections[2025.01]
H10D  62/53  \	2	2	5F121	H10D  62/53	20	ԴȾƳΤˤΡΣ	the imperfections being within the semiconductor body[2025.01]
H10D  62/57  \	2	2	5F121	H10D  62/57	11	ԴȾƳΤɽ̤ˤΡ㡥̤ͭȾƳΡΣ	the imperfections being on the surface of the semiconductor body, e.g. the body having a roughened surface[2025.01]
H10D  62/60  \	1	1	5F121	H10D  62/60	73	Խʪʬۤޤǻ١Σ	Impurity distributions or concentrations[2025.01]
H10D  62/80  \	1	1	5F121	H10D  62/80	572	ħΤΡΣ	characterised by the materials[2025.01]
H10D  62/81  \	2	2	5F121	H10D  62/81	178	̻Ĥ̤򼨤¤ΤΡ㡥ñ̻Ұ͡ŪޤϽŪŰѲĹ¤ΤΡΣ	of structures exhibiting quantum-confinement effects, e.g. single quantum wells; of structures having periodic or quasi-periodic potential variation[2025.01]
H10D  62/81  W	2	0	5F121	H10D  62/81	431	̻Ұ	quantum wells
H10D  62/81  L	2	0	5F121	H10D  62/81	598	̻Һ	quantum wires
H10D  62/81  D	2	0	5F121	H10D  62/81	840	̻ҥɥåȡ̻	quantum dots;quantum islands
H10D  62/81  Z	2	0	5F121	H10D  62/81	1	¾Τ	Others
H10D  62/815  \	3	3	5F121	H10D  62/815	167	ŪޤϽŪŰѲĹ¤ΤΡ㡥ĶʻҤޤ¿̻Ұ͡ΣͣѣסϡΣ	of structures having periodic or quasi-periodic potential variation, e.g. superlattices or multiple quantum wells [MQW][2025.01]
H10D  62/82  \	2	2	5F121	H10D  62/82	71	إƥܹΣ	Heterojunctions[2025.01]
H10D  62/822  \	3	3	5F121	H10D  62/822	335	ɣ²ƱΤΥإƥܹΤߤΡ㡥ӣ顿ǣإƥܹΣ	comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions[2025.01]
H10D  62/824  \	3	3	5F121	H10D  62/824	2079	ɣɣɡ²ƱΤΥإƥܹΤߤΡ㡥ǣΡǣΥإƥܹΣ	comprising only Group III-V materials heterojunctions, e.g. GaN/AlGaN heterojunctions[2025.01]
H10D  62/826  \	3	3	5F121	H10D  62/826	13	ɣɡ֣²ƱΤΥإƥܹΤߤΡ㡥ãԣ塿ȣԣإƥܹΣ	comprising only Group II-VI materials heterojunctions, e.g. CdTe/HgTe heterojunctions[2025.01]
H10D  62/83  \	2	2	5F121	H10D  62/83	263	ɣ²ǤΡ㡥¥ɡףӣޤϥɡףǣΣ	being Group IV materials, e.g. B-doped Si or undoped Ge[2025.01]
H10D  62/832  \	3	3	5F121	H10D  62/832	332	İʾθǤʤɣ²ǤΡ㡥ӣǣΣ	being Group IV materials comprising two or more elements, e.g. SiGe[2025.01]
H10D  62/834  \	3	3	5F121	H10D  62/834	80	˥ɡѥȤˤħΤΡΣ	further characterised by the dopants[2025.01]
H10D  62/84  \	2	2	5F121	H10D  62/84	2	ޤϥƥΤߤǤΡΣ	being selenium or tellurium only[2025.01]
H10D  62/85  \	2	2	5F121	H10D  62/85	393	ɣɣɡ²ǤΡ㡥ǣΣ	being Group III-V materials, e.g. GaAs[2025.01]
H10D  62/852  \	3	3	5F121	H10D  62/852	563	İʾθǤʤɣɣɡ²ǤΡ㡥ǣΤޤϣɣӣСΣ	being Group III-V materials comprising three or more elements, e.g. AlGaN or InAsSbP[2025.01]
H10D  62/854  \	3	3	5F121	H10D  62/854	72	˥ɡѥȤˤħΤΡΣ	further characterised by the dopants[2025.01]
H10D  62/86  \	2	2	5F121	H10D  62/86	48	ɣɡ֣²ǤΡ㡥ڣϡΣ	being Group II-VI materials, e.g. ZnO[2025.01]
H10D  62/862  \	3	3	5F121	H10D  62/862	41	İʾθǤʤɣɡ֣²ǤΡ㡥ãڣԣΣ	being Group II-VI materials comprising three or more elements, e.g. CdZnTe[2025.01]
H10D  62/864  \	3	3	5F121	H10D  62/864	11	˥ɡѥȤˤħΤΡΣ	further characterised by the dopants[2025.01]
H10D  64/00  \	0	0	4M104	H10D  64/00	893	Ű̾ɤ֤ͭŶˡΣ	Electrodes of devices having potential barriers[2025.01]
H10D  64/01  \	1	1	4M104	H10D  64/01	0	¤ޤϽΣ	Manufacture or treatment[2025.01]
H10D  64/01  A	1	0	4M104	H10D  64/01	2159	˴ؤ	in relation to pretreatment
H10D  64/01  B	1	0	4M104	H10D  64/01	1356	˴ؤ	in relation to post treatment
H10D  64/01  C	1	0	4M104	H10D  64/01	141	ޤϸ˴ؤ	in relation to tests or inspections
H10D  64/01  D	1	0	4M104	H10D  64/01	356	Ϫħͭ	characterized by exposure processes
H10D  64/01  E	1	0	4M104	H10D  64/01	3224	å󥰡եȥդޤϸˤ	by etching, lift off or polishing
H10D  64/01  K	1	0	4M104	H10D  64/01	322	ʬŪѼˡˤ	by partial transformation methods
H10D  64/01  L	1	0	4M104	H10D  64/01	3544	Ŷ˼Ѥι˴ؤ	in relation to making holes for removal of electrodes
H10D  64/01  M	1	0	4M104	H10D  64/01	4172	Ƴؤη˴ؤ	in relation to the formation of electricity conducting layers
H10D  64/01  S	1	0	4M104	H10D  64/01	1188	ؤη˴ؤ	in relation to the formation of insulation layers
H10D  64/01  Z	1	0	4M104	H10D  64/01	1225	¾Τ	Others
H10D  64/20  \	1	1	4M104	H10D  64/20	520	Ū礭ޤ֤ħΤŶˡΣ	Electrodes characterised by their shapes, relative sizes or dispositions[2025.01]
H10D  64/20  F	1	0	4M104	H10D  64/20	1786	եɥץ졼	field plates
H10D  64/20  Z	1	0	4M104	H10D  64/20	23	¾Τ	Others
H10D  64/23  \	2	2	4M104	H10D  64/23	91	ήȯޤϥåήήŶˡ㡥ɥ쥤󡤥ΡɤޤϥɡΣ	Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes[2025.01]
H10D  64/23  D	2	0	4M104	H10D  64/23	3626	ѤΤ	for diodes
H10D  64/23  B	2	0	4M104	H10D  64/23	2569	Хݡȥ󥸥ѤΤ	for bipolar transistors
H10D  64/23  M	2	0	4M104	H10D  64/23	9262	ͣɣӤޤϣͣϣӥȥ󥸥ѤΤ	for MISor MOS transistors
H10D  64/23  J	2	0	4M104	H10D  64/23	3571	ܹ緿ޤϣͣţӷѤΤ	for junction types or MES types
H10D  64/23  Z	2	0	4M104	H10D  64/23	6873	¾Τ	Others
H10D  64/27  \	2	2	4M104	H10D  64/27	76	ήȯޤϥåήήʤŶˡ㡥ȡΣ	Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates[2025.01]
H10D  64/27  G	2	0	4M104	H10D  64/27	9033	ͣɣӤޤϣͣϣӥѤΤ	for MIS or MOS gates
H10D  64/27  Z	2	0	4M104	H10D  64/27	2209	¾Τ	Others
H10D  64/60  \	1	1	4M104	H10D  64/60	211	ħΤŶˡΣ	Electrodes characterised by their materials[2025.01]
H10D  64/62  \	2	2	4M104	H10D  64/62	38	ȾƳΤȥߥå³줿ŶˡΣ	Electrodes ohmically coupled to a semiconductor[2025.01]
H10D  64/62  A	2	0	4M104	H10D  64/62	2158	ꥳѤƤ	using silicon
H10D  64/62  D	2	1	4M104	H10D  64/62	812	ꥳŶ˾˥ꥵɤƤ	with silicide formed on silicon electrodes
H10D  64/62  R	2	0	4M104	H10D  64/62	7735	°ޤ϶°ʪѤƤ	using metals or metal compounds
H10D  64/62  S	2	0	4M104	H10D  64/62	4118	ꥵɤѤƤ	using silicide
H10D  64/62  B	2	0	4M104	H10D  64/62	6690	ȾƳΤꥳʳΤ	semiconductor bodies made of the materials other than silicon
H10D  64/62  Z	2	0	4M104	H10D  64/62	1154	¾Τ	Others
H10D  64/64  \	2	2	4M104	H10D  64/64	4894	ȾƳΤФ륷åȥɤŶˡΣ	Electrodes comprising a Schottky barrier to a semiconductor[2025.01]
H10D  64/64  A	2	0	4M104	H10D  64/64	72	ꥳѤƤ	using silicon
H10D  64/64  D	2	1	4M104	H10D  64/64	11	ꥳŶ˾˥ꥵɤƤ	with silicide formed on silicon electrodes
H10D  64/64  R	2	0	4M104	H10D  64/64	729	°ޤ϶°ʪѤƤ	using metals or metal compounds
H10D  64/64  S	2	0	4M104	H10D  64/64	360	ꥵɤѤƤ	using silicide
H10D  64/64  B	2	0	4M104	H10D  64/64	4030	ȾƳΤꥳʳΤ	semiconductor bodies made of the materials other than silicon
H10D  64/64  Z	2	0	4M104	H10D  64/64	85	¾Τ	Others
H10D  64/66  \	2	2	4M104	H10D  64/66	10	Τ𤷤ȾƳΤ̷礵줿ƳΤͭŶˡ㡥ͣɣŶˡΣ	Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes[2025.01]
H10D  64/66  A	2	0	4M104	H10D  64/66	1463	ꥳѤƤ	using silicon
H10D  64/66  D	2	1	4M104	H10D  64/66	1128	ꥳŶ˾˥ꥵɤƤ	with silicide formed on silicon electrodes
H10D  64/66  R	2	0	4M104	H10D  64/66	2964	°ޤ϶°ʪѤƤ	using metals or metal compounds
H10D  64/66  S	2	0	4M104	H10D  64/66	2187	ꥵɤѤƤ	using silicide
H10D  64/66  B	2	0	4M104	H10D  64/66	2202	ȾƳΤꥳʳΤ	semiconductor bodies made of the materials other than silicon
H10D  64/66  Z	2	0	4M104	H10D  64/66	213	¾Τ	Others
H10D  64/68  \	3	3	4M104	H10D  64/68	4671	Ρ㡥ΡħΤΡΣ	characterised by the insulator, e.g. by the gate insulator[2025.01]
H10D  80/00  \	0	0	5F037	H10D  80/00	1	Υ֥饹ޤ롤ʤȤ⣱Ĥ֤롤ʣ֤ΩΡΣ	Assemblies of multiple devices comprising at least one device covered by this subclass[2025.01]
H10D  80/20  \	1	1	5F037	H10D  80/20	12	ξʤȤ⣱Ĥ֤롼ףȣģȣģޤΡ㡥ѥѥų̥ȥ󥸥ޤϥåȥɤޤΩΡΣ	the at least one device being covered by groups H10D 1/00-H10D 48/00, e.g. assemblies comprising capacitors, power FETs or Schottky diodes[2025.01]
H10D  80/30  \	1	1	5F037	H10D  80/30	4	ξʤȤ⣱Ĥ֤롼ףȣģȣģޤΡ㡥ѲϩΥץåΥåפޤΩΡΣ	the at least one device being covered by groups H10D 84/00-H10D 86/00, e.g. assemblies comprising integrated circuit processor chips[2025.01]
H10D  84/00  \	0	0	5F081	H10D  84/00	855	ȾƳؤΤߤȾƳδޤϾ塤㡥ӣ饦Ͼޤϣӣ饦ϾΣǣ塤˷뽸֡Σ	Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers[2025.01]
H10D  84/01  \	1	1	5F081	H10D  84/01	2	¤ޤϽΣ	Manufacture or treatment[2025.01]
H10D  84/02  \	2	2	5F081	H10D  84/02	0	˴ŤѤѤ뤳ȤħΤΡΣ	characterised by using material-based technologies[2025.01]
H10D  84/03  \	3	3	5F081	H10D  84/03	0	ɣ²ѤѤΡ㡥ӣ鵻ѤޤϣӣõѡΣ	using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology[2025.01]
H10D  84/05  \	3	3	5F081	H10D  84/05	0	ɣɣɡ²ѤѤΡΣ	using Group III-V technology[2025.01]
H10D  84/07  \	3	3	5F081	H10D  84/07	0	ɣɡ֣²ѤѤΡΣ	using Group II-VI technology[2025.01]
H10D  84/08  \	3	3	5F081	H10D  84/08	0	ʣεѤȤ߹碌ѤΡ㡥ӣ鵻ѤȣӣõѤξѤΡޤϣӣ鵻Ѥȣɣɣɡ²ѤѤΡΣ	using combinations of technologies, e.g. using both Si and SiC technologies or using both Si and Group III-V technologies[2025.01]
H10D  84/40  \	1	1	5F048	H10D  84/40	372	롼ףȣģޤϣȣģޤ뾯ʤȤ⣱Ĥιʤȡ롼ףȣģޤϣȣģޤ뾯ʤȤ⣱ĤιʤȤνѤħΤΡ㡥Хݡȥ󥸥沈ų̥ȥ󥸥νѡΣ	characterised by the integration of at least one component covered by groups H10D 12/00 or H10D 30/00 with at least one component covered by groups H10D 10/00 or H10D 18/00, e.g. integration of IGFETs with BJTs[2025.01]
H10D  84/40  A	1	0	5F048	H10D  84/40	955	Ρ㡥ʣǻҤ֤ޤˡħΤ	characterized by the whole, e.g., the arrangements or manufacturing methods of plural elements
H10D  84/40  B	1	0	5F048	H10D  84/40	829	Хݡȥ󥸥ιħΤΡʣáʤͥ	characterized by the structures of bipolar transistors (C~J take precedence)
H10D  84/40  C	1	0	5F048	H10D  84/40	323	ǻʬΥ	isolation of elements
H10D  84/40  D	1	0	5F048	H10D  84/40	117	ååɻ	latch-up prevention
H10D  84/40  E	1	0	5F048	H10D  84/40	405	ġ롨	substrates;wells;buried layers
H10D  84/40  F	1	0	5F048	H10D  84/40	199	󥿥ȡŶˡ	contacts;electrodes;wiring
H10D  84/40  G	1	0	5F048	H10D  84/40	357	ϩħΤ	characterized by circuit structures
H10D  84/40  H	1	1	5F048	H10D  84/40	231	Хͣϣʣ絡ǽǻ	BiMOS composite function element
H10D  84/40  J	1	1	5F048	H10D  84/40	334	ѡ㡥ϩ	for specific purposes, e.g., logic circuits, memories
H10D  84/40  Z	1	0	5F048	H10D  84/40	116	¾Τ	Others
H10D  84/60  \	1	1	5F082	H10D  84/60	0	롼ףȣģޤϣȣģޤ뾯ʤȤ⣱ĤιʤνѤħΤΡ㡥Хݡȥ󥸥νѡʣȣģͥˡΣ	characterised by the integration of at least one component covered by groups H10D 10/00 or H10D 18/00, e.g. integration of BJTs (H10D 84/40 takes precedence)[2025.01]
H10D  84/60 101 \	2	2	5F082	H10D  84/60	194	ꥹѤ	integrating thyristors
H10D  84/60 201 \	2	2	5F082	H10D  84/60	38	Хݡȥ󥸥¾ǻҤѤ	integrating bipolar transistors with other elements
H10D  84/60 201 U	2	0	5F082	H10D  84/60	1007	Хݡȥ󥸥ȥ˥ݡȥ󥸥ʤ	comprised of bipolar transistors and unipolar transistors
H10D  84/60 201 S	2	0	5F082	H10D  84/60	295	Хݡȥ󥸥ȣӣɣԤʤϩ	logic circuits composed of bipolar transistors and SIT
H10D  84/60 201 D	2	0	5F082	H10D  84/60	1783	Хݡȥ󥸥ȥѥ񹳤ޤϥɤʤ	composed of bipolar transistors and inductors, capacitors, resistance or diodes
H10D  84/60 201 P	2	0	5F082	H10D  84/60	827	ݸϩ	protection circuits
H10D  84/60 201 Z	2	0	5F082	H10D  84/60	994	¾Τ	Others
H10D  84/60 202 \	2	2	5F082	H10D  84/60	62	Хݡȥ󥸥ΤߤѤ	integrating only bipolar transistors
H10D  84/60 202 B	2	0	5F082	H10D  84/60	331	Хݡȥ󥸥ʤΡʣ̡Ĥͥ	composed of bipolar transistors (L~D take precedence)
H10D  84/60 202 L	2	0	5F082	H10D  84/60	474	Хݡȥ󥸥ʤϩ	logic circuits composed of bipolar transistors
H10D  84/60 202 T	2	0	5F082	H10D  84/60	237	ۤʤХݡȥ󥸥ʤ	composed of bipolar transistors with different traits
H10D  84/60 202 D	2	0	5F082	H10D  84/60	349	ȥ³	Darlington junctions
H10D  84/60 202 Z	2	0	5F082	H10D  84/60	96	¾Τ	Others
H10D  84/63  \	2	2	5F082	H10D  84/63	241	ķХݡȥ󥸥ȲХݡȥ󥸥ȤȤ߹碌Σ	Combinations of vertical and lateral BJTs[2025.01]
H10D  84/65  \	2	2	5F082	H10D  84/65	421	Σɣɣ̡ϡΣ	Integrated injection logic[2025.01]
H10D  84/65  J	2	0	5F082	H10D  84/65	344	󥸥	injectors
H10D  84/65  N	2	0	5F082	H10D  84/65	349	С	inverters
H10D  84/65  W	2	0	5F082	H10D  84/65	415	ɣɣ̤ޤϩ	circuits including IIL
H10D  84/65  Z	2	0	5F082	H10D  84/65	0	¾Τ	Others
H10D  84/67  \	2	2	5F082	H10D  84/67	628	䷿Хݡȥ󥸥Σ	Complementary BJTs[2025.01]
H10D  84/80  \	1	1	5F048	H10D  84/80	8	롼ףȣģޤϣȣģޤ뾯ʤȤ⣱ĤιʤνѤħΤΡ㡥沈ų̥ȥ󥸥νѡʣȣģͥˡΣ	characterised by the integration of at least one component covered by groups H10D 12/00 or H10D 30/00, e.g. integration of IGFETs (H10D 84/40 takes precedence)[2025.01]
H10D  84/80 101 \	2	2	5F048	H10D  84/80	72	沈ų̥ȥ󥸥¾ǻҤѤ	integrating insulation gate field effect transistors with other elements
H10D  84/80 101 A	2	0	5F048	H10D  84/80	5732	沈ų̥ȥ󥸥ȡưǻҤޤϥɤѤ	integrating insulation gate field effect transistors with passive elements or diodes
H10D  84/80 101 Z	2	0	5F048	H10D  84/80	887	¾Τ	Others
H10D  84/80 102 \	3	3	5F048	H10D  84/80	42	ݸϩ	protection circuits
H10D  84/80 102 A	3	0	5F048	H10D  84/80	703	񹳤ѤݸΡ󥿥ħΤ	protected by use of resistance, characterized by contact parts
H10D  84/80 102 B	3	0	5F048	H10D  84/80	1495	ɤѤݸ	protected by use of diodes
H10D  84/80 102 C	3	0	5F048	H10D  84/80	1921	Хݡޤͣϣӹ¤Ѥݸ	protected by use of MOS structures including bipolar
H10D  84/80 102 Z	3	0	5F048	H10D  84/80	270	¾Τ	Others
H10D  84/80 201 \	3	3	5F111	H10D  84/80	0	ķɣǣ£Ԥޤϣ֣ģͣϣӤޤ	Including vertical IGBT or VDMOS
H10D  84/80 202 \	4	4	5F111	H10D  84/80	0	¾Υȥ󥸥ޤ¾ΥѥǻҤȤ߹碌	combined with other transistors or power devices of other kinds
H10D  84/80 202 A	4	0	5F111	H10D  84/80	601	ķȥ󥸥ȤȤ߹碌㡥ȥ֥å	combination with vertical transistors, e.g., H-bridges
H10D  84/80 202 B	4	0	5F111	H10D  84/80	204	ȥ󥸥ȤȤ߹碌	combination with vertical transistors
H10D  84/80 202 C	4	1	5F111	H10D  84/80	203	ͣϣӽѲϩȤȤ߹碌㡥ѥɣ	combination with MOS integrated circuits, e.g., power IC
H10D  84/80 202 D	4	2	5F111	H10D  84/80	87	¤ħΤ	characterized by the structures
H10D  84/80 202 E	4	3	5F111	H10D  84/80	159	ѥʬΥΰ	isolation regions of the power sections and the control sections
H10D  84/80 202 F	4	3	5F111	H10D  84/80	45	ѥ֥ѥ	arrangement patterns of the power sections and the control sections
H10D  84/80 202 G	4	2	5F111	H10D  84/80	69	¤ˡħΤ	characterized by the manufacturing methods
H10D  84/80 202 Z	4	0	5F111	H10D  84/80	70	¾Τ	Others
H10D  84/80 203 \	4	4	5F111	H10D  84/80	2	ݸǻҤޤϲϩȤ߹	incorporating protection elements or protection circuits
H10D  84/80 203 A	4	0	5F111	H10D  84/80	1005	ɤȤ߹	incorporating diodes
H10D  84/80 203 B	4	1	5F111	H10D  84/80	254	ݸ	gate protection diodes
H10D  84/80 203 C	4	2	5F111	H10D  84/80	355	ӣϣɹ¤Τ	SIO structures
H10D  84/80 203 D	4	1	5F111	H10D  84/80	2082	ή	reflux diodes
H10D  84/80 203 E	4	0	5F111	H10D  84/80	115	ȥ󥸥Ȥ߹	incorporating transistors
H10D  84/80 203 F	4	1	5F111	H10D  84/80	804	ưָФΤΥȥ󥸥	transistor cells for detecting operation status
H10D  84/80 203 G	4	0	5F111	H10D  84/80	715	ϩħΤ	characterized by circuit structures
H10D  84/80 203 Z	4	0	5F111	H10D  84/80	227	¾Τ	Others
H10D  84/82  \	2	2	5F048	H10D  84/82	3	ų̹ʤΤߤѤΡΣ	of only field-effect components[2025.01]
H10D  84/83  \	3	3	5F048	H10D  84/83	312	沈ų̥ȥ󥸥ΤߤѤΡΣ	of only insulated-gate FETs [IGFET][2025.01]
H10D  84/83  A	3	0	5F048	H10D  84/83	2005	ͣϣӹ¤Ρ㡥ʣǻҤ֤ޤˡħΤ	characterized by the entire MOS structures, e.g.,  characterized by the arrangement or the manufacturing methods of plural elements
H10D  84/83  B	3	0	5F048	H10D  84/83	2703	ͥ빽¤ޤϥɥ쥤¤	channel structures or source structures, drain structures
H10D  84/83  C	3	0	5F048	H10D  84/83	3107	Ŷˡ	gate electrodes;gate insulating films
H10D  84/83  D	3	0	5F048	H10D  84/83	1702	󥿥ȡŶˡ	contacts;electrodes;wiring
H10D  84/83  E	3	0	5F048	H10D  84/83	4009	طͣϣӡķͣϣ	stacked MOS;vertical MOS
H10D  84/83  F	3	0	5F048	H10D  84/83	1064	ͣϣӣɣäФݸϩ	protection circuits for MOSIC
H10D  84/83  H	3	0	5F048	H10D  84/83	1391	ꡨϩ	memories;logic circuits
H10D  84/83  J	3	0	5F048	H10D  84/83	998	ϩħΤ	characterized by circuit structures
H10D  84/83  Z	3	0	5F048	H10D  84/83	331	¾Τ	Others
H10D  84/83 101 \	4	4	5F048	H10D  84/83	33	ɻߡ㡥ǻʬΥ	prevention of parasitic effects, e.g., isolation of elements
H10D  84/83 101 A	4	0	5F048	H10D  84/83	1726	ʬΥ	isolation of insulation
H10D  84/83 101 B	4	0	5F048	H10D  84/83	680	ͥ륹ȥåѡɥ	channel stoppers;guard rings
H10D  84/83 101 C	4	0	5F048	H10D  84/83	407	ġ	substrates;embedded layers
H10D  84/83 101 D	4	0	5F048	H10D  84/83	408		wells
H10D  84/83 101 E	4	0	5F048	H10D  84/83	5722	ӣϣӡӣϣ	SOS;SOI
H10D  84/83 101 F	4	0	5F048	H10D  84/83	153	ɤޤ񹳤Ѥ	using diodes or resistance
H10D  84/83 101 G	4	0	5F048	H10D  84/83	269	ХͿ	giving biases
H10D  84/83 101 Z	4	0	5F048	H10D  84/83	491	¾Τ	Others
H10D  84/84  \	4	4	5F048	H10D  84/84	93	ϥ󥹥ȥ⡼ɤ沈ų̥ȥ󥸥ӥǥץå⡼ɤ沈ų̥ȥ󥸥Ȥ߹碌Σ	Combinations of enhancement-mode IGFETs and depletion-mode IGFETs[2025.01]
H10D  84/84  A	4	0	5F048	H10D  84/84	355	Ρ㡥ʣǻҤ֤ޤˡħΤ	characterized by the whole, e.g., characterized by the arrangements or manufacturing methods of plural elements
H10D  84/84  Z	4	0	5F048	H10D  84/84	332	¾Τ	Others
H10D  84/85  \	4	4	5F048	H10D  84/85	61	䷿沈ų̥ȥ󥸥㡥ãͣϣӡΣ	Complementary IGFETs, e.g. CMOS[2025.01]
H10D  84/85  A	4	0	5F048	H10D  84/85	1539	ãͣϣΡ㡥ʣǻҤ֤ޤˡħΤ	characterized by the entire CMOS structures, e.g.,  the arrangement or the manufacturing methods of plural elements
H10D  84/85  B	4	0	5F048	H10D  84/85	1977	롨ġ	wells;substrates;embedded layers
H10D  84/85  C	4	0	5F048	H10D  84/85	1662	ͥ빽¤	channel structures
H10D  84/85  D	4	0	5F048	H10D  84/85	3165	Ŷˡ	gate electrodes;gate insulating films
H10D  84/85  E	4	0	5F048	H10D  84/85	1887	ɥ쥤	formation of sources, drains
H10D  84/85  F	4	0	5F048	H10D  84/85	1798	󥿥ȡŶˡ	contacts;electrodes;wiring
H10D  84/85  G	4	0	5F048	H10D  84/85	1154	طͣϣӡķͣϣ	stacked MOS;vertical MOS
H10D  84/85  H	4	0	5F048	H10D  84/85	1046	ãͣϣӤФݸϩ	protection circuits for CMOS
H10D  84/85  K	4	0	5F048	H10D  84/85	745	ꡨϩ	memories;logic circuits
H10D  84/85  L	4	0	5F048	H10D  84/85	1281	ϩħΤ	characterized by the structures of circuits
H10D  84/85  N	4	0	5F048	H10D  84/85	390	¤δά	simplification of manufacturing steps
H10D  84/85  Z	4	0	5F048	H10D  84/85	261	¾Τ	Others
H10D  84/86  \	2	2	5F082	H10D  84/86	1729	åȥɥų̥ȥ󥸥ѤΡΣ	of Schottky-barrier gate FETs[2025.01]
H10D  84/87  \	2	2	5F082	H10D  84/87	809	Уܹ祲ų̥ȥ󥸥ѤΡΣ	of PN-junction gate FETs[2025.01]
H10D  84/90  \	1	1	5F048	H10D  84/90	0	ޥ饤ѲϩΣ	Masterslice integrated circuits[2025.01]
H10D  84/90 101 \	2	2	5F082	H10D  84/90	128	Хݡȥ󥸥ޤླྀѲϩų̥ȥ󥸥ޤླྀѲϩʣͥ	integrated circuits including bipolar transistors;integrated circuits including field effect transistors (102 takes precedence)
H10D  84/90 102 \	2	2	5F048	H10D  84/90	489	沈ų̥ȥ󥸥ޤླྀѲϩ	integrated circuits including insulated gate field effect transistors
H10D  86/00  \	0	0	5F110	H10D  86/00	0	ޤƳޤϾ˷뽸֡㡥ӣϣɴ⡤ޤϥƥ쥹⤷ϥ饹ľ˷ΡΣ	Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates[2025.01]
H10D  86/01  \	1	1	5F110	H10D  86/01	1	¤ޤϽΣ	Manufacture or treatment[2025.01]
H10D  86/01 101 \	2	2	5F110	H10D  86/01	1953	ƥ֥ޥȥꥯΥѥ˥󥰤ħΤ	characterized by the patterning of active matrix
H10D  86/03  \	2	2	5F110	H10D  86/03	524	ĤեʤΡ㡥ӣϣӡΣ	wherein the substrate comprises sapphire, e.g. silicon-on-sapphire [SOS][2025.01]
H10D  86/40  \	1	1	5F110	H10D  86/40	7	ʣȥ󥸥ħΤΡΣ	characterised by multiple TFTs[2025.01]
H10D  86/40 101 \	2	2	5F110	H10D  86/40	28	ͣϣӣɣäѤ	used for MOSIC
H10D  86/40 101 A	2	0	5F110	H10D  86/40	2119	ãͣϣ	CMOS
H10D  86/40 101 B	2	0	5F110	H10D  86/40	2765		memories
H10D  86/40 101 Z	2	0	5F110	H10D  86/40	3335	¾Τ	Others
H10D  86/40 102 \	2	2	5F110	H10D  86/40	1012	ϩħΤΡ㡥ƥ֥ޥȥꥯϩ	characterized by circuit structures, e.g., active matrix circuits per se
H10D  86/60  \	2	2	5F110	H10D  86/60	57	ʣȥ󥸥ƥ֥ޥȥꥯ¸ߤΡΣ	wherein the TFTs are in active matrices[2025.01]
H10D  86/60  A	2	0	5F110	H10D  86/60	1085	ǻҤޤη٤ɻߤޤϽ	pretension or correction of defects of elements or wiring
H10D  86/60  B	2	0	5F110	H10D  86/60	2398	ղϩȰΤ˷줿	formed with peripheral circuits in integrated manners
H10D  86/60  C	2	0	5F110	H10D  86/60	3634	ħΤ	characterized by wiring
H10D  86/60  Z	2	0	5F110	H10D  86/60	2680	¾Τ	Others
H10D  86/80  \	1	1	5F081	H10D  86/80	209	ʣμưʡ㡥񹳴ѥޤϥħΤΡΣ	characterised by multiple passive components, e.g. resistors, capacitors or inductors[2025.01]
H10D  86/85  \	2	2	5F081	H10D  86/85	1729	ưʤΤߤħΤΡΣ	characterised by only passive components[2025.01]
H10D  86/85 101 \	3	3	5F081	H10D  86/85	920	ϩ	thick film circuits
H10D  86/85 102 \	3	3	5F081	H10D  86/85	728	ϩ	thin film circuits
H10D  86/85 103 \	3	3	5F081	H10D  86/85	758	ȥߥ󥰡ȥߥ	thick film trimming;thin film trimming
H10D  87/00  \	0	0	5F048	H10D  87/00	2368	ƱľΥХ륯ʤȣӣϣɤޤϣӣϣӹʤ뽸֡Σ	Integrated devices comprising both bulk components and either SOI or SOS components on the same substrate[2025.01]
H10D  88/00  \	0	0	5F080	H10D  88/00	23	֡Σ	Three-dimensional [3D] integrated devices[2025.01]
H10D  88/00  A	0	0	5F080	H10D  88/00	615	ǻ֤ħΤط	stacked layer types characterized by the arrangements of elements
H10D  88/00  C	0	1	5F080	H10D  88/00	618	³¤	junction structures
H10D  88/00  H	0	1	5F080	H10D  88/00	83	Ǯ¤ɹ¤	heat-releasing structures;shield structures
H10D  88/00  R	0	1	5F080	H10D  88/00	284	Ʒ뾽	recrystallisation technologies
H10D  88/00  N	0	1	5F080	H10D  88/00	38	ȾƳΣز߷	types in which semiconductor i-layers are interposed
H10D  88/00  D	0	1	5F080	H10D  88/00	126	ñ뾽ز߷	types in which single crystal insulator layers are interposed
H10D  88/00  E	0	1	5F080	H10D  88/00	35	ñ뾽ľĹ	technologies for direct growth of single crystal
H10D  88/00  S	0	1	5F080	H10D  88/00	96	ӣɣͣϣ	SIMOX
H10D  88/00  L	0	1	5F080	H10D  88/00	24	ޤ߻	oxidization from below
H10D  88/00  F	0	1	5F080	H10D  88/00	55	ƣɣУϣ	FIPOS
H10D  88/00  P	0	1	5F080	H10D  88/00	63	ݥꥢեط	polyamorphous stacked layer type
H10D  88/00  Y	0	1	5F080	H10D  88/00	58	¾ι¤	Other structures
H10D  88/00  B	0	0	5F080	H10D  88/00	934	巿	adhesive bonding type
H10D  88/00  W	0	0	5F080	H10D  88/00	116	ξ̷	double-sided type
H10D  88/00  Z	0	0	5F080	H10D  88/00	39	¾Τ	Others
H10D  89/00  \	0	0	5F038	H10D  89/00	8	롼ףȣģȣģޤʤ֤δΣ	Aspects of integrated devices not covered by groups H10D 84/00-H10D 88/00[2025.01]
H10D  89/00 101 \	1	1	5F038	H10D  89/00	953	ȾƳν֤ι¤ޤ֤ħΤΡʥ쥤ˡϣͥ	characterized by the structures or arrangements of integrated semiconductor devices ( for layout methods, 89/10 takes precedence)
H10D  89/00 101 A	1	0	5F038	H10D  89/00	6771	ǽϩ㡥ʥϩƥȲϩ֡ʣ¡դͥ	arrangements of functional circuits, e.g., analogue circuits, test circuits (B~U take precedence)
H10D  89/00 101 B	1	0	5F038	H10D  89/00	1946	Űȯϩ㡥ģŸϩ	arrangements of reference voltage generators, e.g., DC power supply circuits
H10D  89/00 101 D	1	0	5F038	H10D  89/00	5647	㡥åŸ	arrangements of wiring, e.g., clock wiring, power supply wiring
H10D  89/00 101 E	1	0	5F038	H10D  89/00	2775	üҤ֤ޤüҤεǽħŤ뵡ǽϩ	arrangements of external signal terminals or arrangements of the functional circuits characterizing the functions of the terminals
H10D  89/00 101 F	1	0	5F038	H10D  89/00	2976	ϩǽưԡɡưħΤ뵡ǽϩ㡥ĥС®®ϩ֥å󥵼ղϩ	arrangements of functional circuits characterized by their circuit functions, operating speed, operating conditions, e.g., arrangements of AD combaters, high-speed/ low-speed circuit blocks, sensor-peripheral circuits
H10D  89/00 101 G	1	0	5F038	H10D  89/00	2042	ĥХȯϩޤϾϩ㡥Ÿѥ㡼ݥײϩ	arrangements of substrate bias generation circuits or booster circuits, e.g., arrangements of power-supply charge pump circuits
H10D  89/00 101 M	1	0	5F038	H10D  89/00	1168	ڤؤưԤǽϩ֡ʣԤͥ	arrangements of functional circuits performing switching operations (T takes precedence)
H10D  89/00 101 T	1	0	5F038	H10D  89/00	7004	ƥȵǽϩϩ	arrangements of test functional circuits, inspection circuits
H10D  89/00 101 U	1	0	5F038	H10D  89/00	1175	ʣεǽϩȤ߹碌㡥ƥ̣ӣɡ	combination of plural functional circuits, e.g., arrangements of system LSIs
H10D  89/00 101 V	1	0	5F038	H10D  89/00	2114	ѥԡǻҤޤϥȥߥǻҤι¤	structures of variable impedance elements or trimming elements
H10D  89/00 101 Z	1	0	5F038	H10D  89/00	531	¾Τ	Others
H10D  89/10  \	1	1	5F064	H10D  89/10	876	֤Υ쥤ȡΣ	Integrated device layouts[2025.01]
H10D  89/10  D	1	0	5F064	H10D  89/10	1701	ǻ߷	designs of elements
H10D  89/10  A	1	1	5F064	H10D  89/10	1419	ץޥ֥å쥤ΣУ̣	programmable logic arrays[PLA]
H10D  89/10  B	1	1	5F064	H10D  89/10	2305	ӥǥ󥰥֥åɥ	Building Blocks;standard cells
H10D  89/10  M	1	1	5F064	H10D  89/10	3538	ޥ饤ȥ쥤	master slice;gate arrays
H10D  89/10  W	1	0	5F064	H10D  89/10	3515	߷	designs of wiring
H10D  89/10  C	1	1	5F064	H10D  89/10	5349	Żҷ׻㡥ãġѤ	using electric computer, e.g., CAD
H10D  89/10  L	1	1	5F064	H10D  89/10	1679	Ÿ	power supply lines
H10D  89/10  P	1	1	5F064	H10D  89/10	1827	ѥåɡϥ	pads;input cells
H10D  89/10  S	1	1	5F064	H10D  89/10	708	ǽ	selection of functions
H10D  89/10  F	1	2	5F064	H10D  89/10	2437	ե塼ʣҡԤͥ	fuses (R,T take precedence)
H10D  89/10  R	1	2	5F064	H10D  89/10	1599	Ĺϩ	redundancy circuits
H10D  89/10  T	1	2	5F064	H10D  89/10	2289		inspections
H10D  89/10  Z	1	0	5F064	H10D  89/10	94	¾Τ	Others
H10D  89/60  \	1	1	5F038	H10D  89/60	9669	ŵޤǮݸ֡㡥šΣţӣġϤݸϩ뽸֡Σ	Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD][2025.01]
H10D  99/00  \	0	0	5F121	H10D  99/00	0	Υ֥饹¾Υ롼פʬवʤΣ	Subject matter not provided for in other groups of this subclass[2025.01]
