H10B  10/00		ƥåॢΣӣң֡͡Σ	Static random access memory [SRAM] devices	9197
H10B  10/10		Хݡ鹽ʤʤӣң֡Σ	SRAM devices comprising bipolar components	25
H10B  12/00		ʥߥåॢΣģң֡͡Σ	Dynamic random access memory [DRAM] devices	43618
H10B  12/10		Хݡ鹽ʤʤģң֡Σ	DRAM devices comprising bipolar components	76
H10B  20/00		ɤ߽ФѥΣңϣ֡͡Σ	Read-only memory [ROM] devices	10023
H10B  20/10		Хݡ鹽ʤʤңϣ֡Σ	ROM devices comprising bipolar components	6
H10B  20/20		ų̹ʤʤ񤭹߲ǽʣңϣ͡ΣУңϣ֡͡ʣȣ£ͥˡΣ	Programmable ROM [PROM] devices comprising field-effect components(<b>H10B20/10</b> takes precedence)	175
H10B  20/25		Τ߽񤭹߲ǽʣңϣ͡ΣϣԣУңϣ֡͡㡥ŵŪǲǽʥ󥯤ѤΡΣ	One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links	394
H10B  41/00		եƥ󥰥ȤޤŵŪõ񤭹߲ǽʣңϣ͡ΣţţУңϣ֡͡Σ	Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates	871
H10B  41/10		夫鸫쥤ȤħΤΡΣ	characterised by the top-view layout	2152
H10B  41/20		֡㡥ۤʤ⤵֤줿롤ħΤΡΣ	characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels	2273
H10B  41/23		ۤʤ⤵Υȥɥ쥤ͭΡ㡥ХͥͭΡΣ	with source and drain on different levels, e.g. with sloping channels	95
H10B  41/27		ľʬޤͥ롤㡥ջͥΣ	the channels comprising vertical portions, e.g. U-shaped channels	5743
H10B  41/30		ꥳΰħΤΡΣ	characterised by the memory core region	3042
H10B  41/35		ȥ󥸥ͭΡ㡥ΣΣġΣ	with a cell select transistor, e.g. NAND	4805
H10B  41/40		ղϩΰħΤΡΣ	characterised by the peripheral circuit region	1723
H10B  41/41		ΰ˥ȥ󥸥ͭΡ㡥ΣΣġΣ	of a memory region comprising a cell select transistor, e.g. NAND	1851
H10B  41/42		ե뤪ӥꥻƱ¤Σ	Simultaneous manufacture of periphery and memory cells	481
H10B  41/43		եȥ󥸥ΤߴޤΡΣ	comprising only one type of peripheral transistor	86
H10B  41/44		ȥ륲ؤեȥ󥸥ΰȤƤѤΡΣ	with a control gate layer also being used as part of the peripheral transistor	138
H10B  41/46		ȴͶؤեȥ󥸥ΰȤƤѤΡΣ	with an inter-gate dielectric layer also being used as part of the peripheral transistor	65
H10B  41/47		եƥ󥰥ؤեȥ󥸥ΰȤƤѤΡΣ	with a floating-gate layer also being used as part of the peripheral transistor	62
H10B  41/48		ȥͥͶؤեȥ󥸥ΰȤƤѤΡΣ	with a tunnel dielectric layer also being used as part of the peripheral transistor	59
H10B  41/49		ۤʤμեȥ󥸥ޤΡΣ	comprising different types of peripheral transistor	174
H10B  41/50		ȼղϩΰȤδ֤ζΰħΤΡΣ	characterised by the boundary region between the core region and the peripheral circuit region	1757
H10B  41/60		ȥ륲ȤɡΰǤΡ㡥ñإݥꥻΣ	the control gate being a doped region, e.g. single-poly memory cell	189
H10B  41/70		եƥ󥰥ȤʣιʤǶͭŶˤǤΡΣ	the floating gate being an electrode shared by two or more components	954
H10B  43/00		Ų٥ȥåԥ󥰥ΤޤţţУңϣ֡Σ	EEPROM devices comprising charge-trapping gate insulators	600
H10B  43/10		夫鸫쥤ȤħΤΡΣ	characterised by the top-view layout	3238
H10B  43/20		֡㡥ۤʤ⤵֤줿롤ħΤΡΣ	characterised by three-dimensional [3D] arrangements, e.g. with cells on different height levels	2956
H10B  43/23		ۤʤ⤵Υȥɥ쥤ͭΡ㡥ХͥͭΡΣ	with source and drain on different levels, e.g. with sloping channels	147
H10B  43/27		ľʬޤͥ롤㡥ջͥΣ	the channels comprising vertical portions, e.g. U-shaped channels	8825
H10B  43/30		ꥳΰħΤΡΣ	characterised by the memory core region	2657
H10B  43/35		ȥ󥸥ͭΡ㡥ΣΣġΣ	with cell select transistors, e.g. NAND	6474
H10B  43/40		ղϩΰħΤΡΣ	characterised by the peripheral circuit region	3932
H10B  43/50		ȼղϩΰȤδ֤ζΰħΤΡΣ	characterised by the boundary region between the core and peripheral circuit regions	2922
H10B  51/00		ͶΥȥ󥸥ޤදͶΥΣƣң֡͡Σ	Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory transistors	362
H10B  51/10		夫鸫쥤ȤħΤΡΣ	characterised by the top-view layout	362
H10B  51/20		֡㡥ۤʤ⤵֤줿롤ħΤΡΣ	characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels	885
H10B  51/30		ꥳΰħΤΡΣ	characterised by the memory core region	1286
H10B  51/40		ղϩΰħΤΡΣ	characterised by the peripheral circuit region	254
H10B  51/50		ȼղϩΰȤδ֤ζΰħΤΡΣ	characterised by the boundary region between the core and peripheral circuit regions	141
H10B  53/00		ͶΥꥭѥޤදͶΥΣƣң֡͡Σ	Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors	445
H10B  53/10		夫鸫쥤ȤħΤΡΣ	characterised by the top-view layout	160
H10B  53/20		֡㡥ۤʤ⤵֤줿롤ħΤΡΣ	characterised by the three-dimensional [3D] arrangements, e.g. with cells on different height levels	526
H10B  53/30		ꥳΰħΤΡΣ	characterised by the memory core region	1200
H10B  53/40		ղϩΰħΤΡΣ	characterised by the peripheral circuit region	228
H10B  53/50		ȼղϩΰȤδ֤ζΰħΤΡΣ	characterised by the boundary region between the core and peripheral circuit regions	94
H10B  61/00		֡㡥񹳣ң͡Σͣң֡͡Σ	Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices	2709
H10B  63/00		Ѳ֡㡥񹳣ң͡Σңң֡͡Σ	Resistance change memory devices, e.g. resistive RAM [ReRAM] devices	2619
H10B  63/10		Ѳң͡ΣУãң͡Уң֡͡Σ	Phase change RAM [PCRAM, PRAM] devices	1108
H10B  69/00		롼ףȣ£ȣ£ޤʤõǽǥץǽʣңϣ͡ΣţУңϣ֡͡㡥糰ˤõǽǥץǽʣңϣ͡Σգ֣ţУңϣ֡͡Σ	Erasable-and-programmable ROM [EPROM] devices not provided for in groups <b>H10B41/00 to H10B63/00</b> , e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices	27832
H10B  80/00		Υ֥饹ޤ롤ʤȤ⣱Ĥε֤롤ʣ֤ΩΡΣ	Assemblies of multiple devices comprising at least one memory device covered by this subclass	3589
H10B  99/00		Υ֥饹¾Υ롼פʬवʤΣ	Subject matter not provided for in other groups of this subclass	3218
