H10W  10/00		֤ιʴ֤ˤȾƳʬΥΰΣ	Isolation regions in semiconductor bodies between components of integrated devices	
H10W  10/10		ͶźޤʬΥΰΣ	Isolation regions comprising dielectric materials	
H10W  10/13		ꥳζɽΣ̣ϣãϣӡϤˤΡ㡥̶߳ɽΣӣɣ̣ϡϤޤ¦ɥޥʬΥΣӣףͣɡϡΣ	formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]	
H10W  10/17		ͶźѤȥƽŶˤΡ㡥ȥʬΥΣ	formed using trench refilling with dielectric materials, e.g. shallow trench isolations	
H10W  10/20		åסΣ	Air gaps	
H10W  10/30		УܹޤʬΥΰΣ	Isolation regions comprising PN junctions	
H10W  10/40		¿뾽ȾƳκޤʬΥΰΣ	Isolation regions comprising polycrystalline semiconductor materials	
H10W  10/50		ų̤˴ŤʬΥΰΣ	Isolation regions based on field-effect	
H10W  15/00		֤ιǻ٤˥ɡפ줿ΰΣ	Highly-doped buried regions of integrated devices	
H10W  20/00		åסϤޤϴĤˤ³Σ<br><br><b><ul></ul></b><br>Σ<br>Υ롼פϰʲΤΤޤ롧<br>å³<br>ޤϥϾ³<br>ޤϴľ³<br>Υ롼פϥ֥롼ףȣףޤϣȣףޤ롤ѥåޤϾʤɤΡѥå³ޤʤ	Interconnections in chips, wafers or substrates; <br><br><b><u>Note(s)</u></b><br><br><ul><li>This group <u>covers</u>: <ul><li>interconnections in chips;</li><li>interconnections in or on wafers;</li><li>interconnections in or on substrates.</li></ul></li><li>This group <u>does not cover</u> interconnections in packages, such as in or on package substrates, which are covered by subgroups <b>H10W70/00</b> or <b>H10W72/00</b>.</li></ul>	
H10W  20/20		ޤϴˤ³㡥ꥳ̥ӥΣԣӣ֡ϡΣ	Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]	
H10W  20/40		Ϥγ¦ޤϴĤγ¦ˤ³㡥ХåΣ£ţϣ̡ϤΥ᥿饤ޤϥŶˤ³ƤӥΣ	Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes	
H10W  20/41		ƳʬħΤΡΣ	characterised by their conductive parts	
H10W  20/42		ӥ㡥ӥץ饰Σ	Vias, e.g. via plugs	
H10W  20/43		³Υ쥤ȡΣ	Layouts of interconnections	
H10W  20/44		ƳʬƳźħΤΡΣ	Conductive materials thereof	
H10W  20/45		ʬħΤΡΣ	characterised by their insulating parts	
H10W  20/46		åפޤΡΣ	comprising air gaps	
H10W  20/47		ۤʤ㡥ۤʤͶΨͭ룲İʾͶؤޤΡΣ	comprising two or more dielectric layers having different properties, e.g. different dielectric constants	
H10W  20/48		ʬħΤΡΣ	Insulating materials thereof	
H10W  20/49		ŬѲǽ³㡥ҥ塼ޤϥҥ塼Σ	Adaptable interconnections, e.g. fuses or antifuses	
H10W  29/00		¾ʬवʤ֤ΰŪʡΣ	Generic parts of integrated devices, not otherwise provided for	
H10W  40/00		ǮݸޤǮΤιǮݸ֤뽸֣ȣģˡΣ	Arrangements for thermal protection or thermal control(integrated devices comprising arrangements for thermal protection <b>H10D89/60</b>)	
H10W  40/10		ǮΤιΣ	Arrangements for heating	
H10W  40/20		ѤΤιΣ	Arrangements for cooling	
H10W  40/22		ѤΤιηħΤΡ㡥߿ޤϱͽͭΡΣ	characterised by their shape, e.g. having conical or cylindrical projections	
H10W  40/25		ѤΤικħΤΡΣ	characterised by their materials	
H10W  40/28		ڥ顼ޤΡΣ	comprising Peltier coolers	
H10W  40/30		ѥåΤʳή˿ƤΡ㡥㲹ήΤ˿ƤΡΣ	wherein the packaged device is completely immersed in a fluid other than air, e.g. immersed in a cryogenic fluid	
H10W  40/40		ήưήΤˤǮ򴹤ȼΡΣ	involving heat exchange by flowing fluids	
H10W  40/43		ήưΤˤΡ㡥Σ	by flowing gases, e.g. forced air cooling	
H10W  40/47		ήưΤˤΡ㡥Σ	by flowing liquids, e.g. forced water cooling	
H10W  40/50		٤Τ뤿ιΣ	Arrangements for sensing temperature	
H10W  40/60		ǮޤѹʬΥǽ˼դʡ㡥סΣ	Securing means for detachable heating or cooling arrangements, e.g. clamps	
H10W  40/70		ƴޤˤ롤ǮݸޤǮΤνŶޤΣ	Fillings or auxiliary members in containers or in encapsulations for thermal protection or control	
H10W  40/73		ѲˤѡΣ	for cooling by change of state	
H10W  40/77		ħΤΣ	Auxiliary members characterised by their shape	
H10W  40/80		ѥåǮݸޤǮΤβϩΣ	Circuit arrangements for thermal protection or control of packages	
H10W  42/00		֤ݸΤιǮݸΤιȣףˡΣ	Arrangements for protection of devices(arrangements for thermal protection <b>H10W40/00</b>)	
H10W  42/20		żȤޤγݸ㡥ޤŻҡΣ	protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons	
H10W  42/25		եݸ㡥ѤΤΤΡΣ	against alpha rays, e.g. for outer space applications	
H10W  42/40		󤫤ݸ㡥ʸޤϥС󥸥˥󥰤ݸΣ	protecting against tampering, e.g. unauthorised inspection or reverse engineering	
H10W  42/60		Ų٤ޤŵŤݸ㡥եǡɡŵݸ֤뽸֡ȣģˡΣ	protecting against electrostatic charges or discharges, e.g. Faraday shields (integrated devices comprising arrangements for electrical protection <b>H10D89/60</b>)	
H10W  42/80		ήޤϲ٤ݸ㡥ҥ塼ޤʬήŵݸ֤뽸֡ȣģˡΣ	protecting against overcurrent or overload, e.g. fuses or shunts (integrated devices comprising arrangements for electrical protection <b>H10D89/60</b>)	
H10W  44/00		ԡ󥹤ޤ礵뤿ŵŪΣ	Electrical arrangements for controlling or matching impedance	
H10W  44/20		ȿΣȣơϤޤ̵ȿΣңơϤˤŵŪΣ	at high-frequency [HF] or radio frequency [RF]	
H10W  46/00		֤ŬѤޡ㡥ޤϼ̤뤿ΤΡΣ<br><br><b><ul></ul></b><br>Σ<br>Υ롼פϡåסϡġѥåޤϾˤޡޤ롣	Marks applied to devices, e.g. for alignment or identification; <br><br><b><u>Note(s)</u></b><br><br><ul><li>This group <u>covers</u> marks in or on chips, wafers, substrates or packages. </li></ul>	
H10W  70/00		ѥåġ󥿡ݡءΣңģ̡ϡΣ	Package substrates; Interposers; Redistribution layers [RDL]	
H10W  70/01		¤ޤϽΣ	Manufacture or treatment	
H10W  70/02		ȤƵǽƳѥåĤ¤ޤϽ㡥°ġʥ꡼ɥե졼¤ޤϽȣףˡΣ	of conductive package substrates serving as an interconnection, e.g. of metal plates(manufacture or treatment of leadframes <b>H10W70/04</b>)	
H10W  70/04		꡼ɥե졼¤ޤϽΣ	of leadframes	
H10W  70/05		ѥåġ󥿡ݡޤϺؤ¤ޤϽʥ꡼ɥե졼¤ޤϽȣףˡΣ	of insulating or insulated package substrates, or of interposers, or of redistribution layers(manufacture or treatment of leadframes <b>H10W70/04</b>)	
H10W  70/06		ŪٻΤѤΡΣ	using temporary auxiliary supports	
H10W  70/08		åפޤϥϾؤѤΡ㡥åץեȣңģ̡Σ	by depositing layers on the chip or wafer, e.g. "chip-first" RDLs	
H10W  70/09		åפޤϥϤβϤȤξرĹΡ㡥ե󥢥ȥϥ٥ѥåΣƣϣף̣Сϣңģ̡Σ	extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs	
H10W  70/20		ȤƵǽƳѥåġ㡥°ġʥ꡼ɥե졼ȣףˡΣ	Conductive package substrates serving as an interconnection, e.g. metal plates(leadframes <b>H10W70/40</b>)	
H10W  70/40		꡼ɥե졼Σ	Leadframes	
H10W  70/60		ѥåġ󥿡ݡءʥ꡼ɥե졼ࡡȣףˡΣ	Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes <b>H10W70/40</b>)	
H10W  70/62		ѥåġ󥿡ݡޤϺؤħΤΡΣ	characterised by their interconnections	
H10W  70/63		ӥ㡥ӥץ饰Σ	Vias, e.g. via plugs	
H10W  70/65		ηޤ֡Σ	Shapes or dispositions of interconnections	
H10W  70/652		̷Σ	Cross-sectional shapes	
H10W  70/654		̻Υ쥤ȡΣ	Top-view layouts	
H10W  70/655		ե󥢥ȤΥ쥤ȡΣ	Fan-out layouts	
H10W  70/656		ե󥤥Υ쥤ȡΣ	Fan-in layouts	
H10W  70/66		ƳźħΤΡΣ	Conductive materials thereof	
H10W  70/67		ѥåġ󥿡ݡޤϺؤؤޤʬħΤΡΣ	characterised by their insulating layers or insulating parts	
H10W  70/68		ؤޤʬηޤ֡Σ	Shapes or dispositions thereof	
H10W  70/685		ʣؤޤޤ֡Σ	comprising multiple insulating layers	
H10W  70/69		ؤޤʬħΤΡΣ	Insulating materials thereof	
H10W  70/692		ߥåޤϥ饹Σ	Ceramics or glasses	
H10W  70/695		ͭΣ	Organic materials	
H10W  70/698		ŵŪ魯ȾƳκ㡥ɡץꥳΣ	Semiconductor materials that are electrically insulating, e.g. undoped silicon	
H10W  72/00		ѥå³ޤϥͥΣ<br><br><b><ul></ul></b><br>Σ<br>Υ롼פˤƤϡܥɥѥåɰ̡ʤϢ륳ͥꤵʤޤʣμΥͥФŪʾ硤ϥ롼ףȣףʬव롣μΥͥäŬ礹ܥɥѥåɤϡΥͥμޤ륰롼פʬव롣㤨С磻䥳ͥäŬ礹ܥɥѥåɤϥ롼ףȣףʬव롣	Interconnections or connectors in packages; <br><br><b><u>Note(s)</u></b><br><br><ul><li>In this group, bond pads in general, i.e. where the nature of a related connector is unspecified or generic to multiple types of connectors, are classified in group <b>H10W72/90</b>. Bond pads specially adapted for a specific type of connector are classified in the group covering the connector type. For example, bond pads specially adapted for wire connectors are classified in group <b>H10W72/59</b>.</li></ul>	
H10W  72/20		Хץͥ㡥ϤХפޤƼԥ顼ߡХסޥХסΣ	Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps	
H10W  72/29		ΤäŬ礹ܥɥѥåɡΣ	Bond pads specially adapted therefor	
H10W  72/30		åͥΣ	Die-attach connectors	
H10W  72/40		ƳΣ	Anisotropic conductive adhesives	
H10W  72/49		ΤäŬ礹ܥɥѥåɡΣ	Bond pads specially adapted therefor	
H10W  72/50		ܥɥ磻Σ	Bond wires	
H10W  72/59		ΤäŬ礹ܥɥѥåɡΣ	Bond pads specially adapted therefor	
H10W  72/60		ȥåץͥ㡥֤Ϥ뤿θƼåסΣ	Strap connectors, e.g. thick copper clips for grounding of power devices	
H10W  72/90		ܥɥѥåɰ̡Σ	Bond pads, in general	
H10W  74/00		ȡ㡥ݸʤΣ	Encapsulations, e.g. protective coatings	
H10W  74/01		¤ޤϽΣ	Manufacture or treatment	
H10W  74/10		Ȥηޤ֤ħΤΡΣ	characterised by their shape or disposition	
H10W  74/15		եåץå֤γɽ̤ξˤΡ㡥եΣ	on active surfaces of flip-chip devices, e.g. underfills	
H10W  74/40		ȤκħΤΡΣ	characterised by their materials	
H10W  74/43		ʪⲽʪޤúʪޤΡ㡥ߥåޤϥ饹Σ	comprising oxides, nitrides or carbides, e.g. ceramics or glasses	
H10W  74/47		ͭޤΡ㡥Σ	comprising organic materials, e.g. plastics or resins	
H10W  76/00		ƴŶޤϤΤࡨΣ	Containers; Fillings or auxiliary members therefor; Seals	
H10W  76/01		¤ޤϽΣ	Manufacture or treatment	
H10W  76/05		ƴؤνŶ㡥ŶΣ	Providing fillings in containers, e.g. gas filling	
H10W  76/10		ƴޤϤʬΣ	Containers or parts thereof	
H10W  76/12		ƴηħΤΡΣ	characterised by their shape	
H10W  76/13		ȤƵǽƳޤƴΣ	Containers comprising a conductive base serving as an interconnection	
H10W  76/132		Ƴϩ̤¾ͭΡΣ	having other interconnections through an insulated passage in the conductive base	
H10W  76/134		ƳФʿԤ¾ͭΡΣ	having other interconnections parallel to the conductive base	
H10W  76/136		ƳФƿľ¾ͭΡΣ	having other interconnections perpendicular to the conductive base	
H10W  76/138		ƳФʿԤʤĤˤ¾ͭΡ㡥ɥåΣ	having another interconnection being formed by a cover plate parallel to the conductive base, e.g. sandwich type	
H10W  76/15		ޤƴΣ	Containers comprising an insulating or insulated base	
H10W  76/153		̤ϩͭΡΣ	having interconnections in passages through the insulating or insulated base	
H10W  76/157		ФʿԤͭΡΣ	having interconnections parallel to the insulating or insulated base	
H10W  76/17		ƴκħΤΡΣ	characterised by their materials	
H10W  76/18		㡥顤饹ޤϥߥåΣ	Insulating materials, e.g. resins, glasses or ceramics	
H10W  76/40		ƴνŶޤࡤ㡥󥿥ƴޤˤ롤ǮݸޤǮΤνŶޤࡡȣףˡΣ	Fillings or auxiliary members in containers, e.g. centering rings (fillings or auxiliary members for thermal protection or control in containers or encapsulations <b>H10W40/70</b>)	
H10W  76/42		ŶΣ<br><br><b><ul></ul></b><br>Σ<br>Υ롼פǤϡŶ֤ư٤Ƿꤵ	Fillings; <br><br><b><u>Note(s)</u></b><br><br><ul><li>In this group, the phase of the fillings is determined at the operating temperature of the device. </li></ul>	
H10W  76/43		νŶΣ	Gaseous fillings	
H10W  76/45		վνŶΣ	Liquid fillings	
H10W  76/47		ΤޤϥνŶΣ	Solid or gel fillings	
H10W  76/48		ޤ¾˾ޤʤʪۼ롤ޤϤȿޤོŶΣ	Fillings including materials for absorbing or reacting with moisture or other undesired substances	
H10W  76/60		Σ	Seals	
H10W  76/63		ηޤ֤ħΤΡ㡥ƴγɤδ֤ΥΣ	characterised by their shape or disposition, e.g. between cap and walls of a container	
H10W  76/67		κħΤΡΣ	characterised by their materials	
H10W  78/00		ưΥѥåٻ뤿ʬΥǽݻΣ	Detachable holders for supporting packaged chips in operation	
H10W  80/00		åסϤޤϴĤΥ쥯ȥܥǥ󥰡Σ<br><br><b><ul></ul></b><br>Σ<br>Υ롼פϰʲΥ쥯ȥܥǥ󥰤ޤ롧<br>åƱΡ㡥åסݥȥݥåס<br>֤³ޤϾͭ륦ƱΡ㡥ϡݥȥݥϡ<br>֤³ޤϾͭƱΡ<br>Ȥ߹碌㡥åסݥȥݥϡ	Direct bonding of chips, wafers or substrates; <br><br><b><u>Note(s)</u></b><br><br><ul><li>This group <u>covers</u> direct bonding of:<ul><li>chips, e.g. chip-to-chip;</li><li>wafers having devices and interconnections therein or thereon, e.g. wafer-to-wafer;</li><li>substrates having devices and interconnections therein or thereon;</li><li>combinations thereof, e.g. chip-to-wafer.</li></ul></li></ul>	
H10W  90/00		ѥåƱΤŪϥѥåƱΤŪ֡Σ<br><br><b><ul></ul></b><br>Σ<br>Υ롼פϰʲΤΤޤ롧<br>ñΥѥåˤʣΥåפа֡㡥ñˤܤʣΥåס<br>ʣΥѥåˤʣΥåפа֡㡥֥ѥåݥݥѥå׹ˤȤ줿åפ¾Ȥ줿å׾ˤΡ	Package configurations; <br><br><b><u>Note(s)</u></b><br><br><ul><li>This group <u>covers</u>:<ul><li>the relative positions of multiple chips within a single package, e.g. adjacent chips in a single encapsulation;</li><li>the relative positions of multiple chips within multiple packages, e.g. one encapsulated chip on another encapsulated chip in a "package-on-package" configuration.</li></ul></li></ul>	
H10W  90/10		ܤåפ֡Σ	Configurations of laterally-adjacent chips	
H10W  90/15		ܤåפߤ˰ۤʤߤͭΡΣ	the laterally-adjacent chips having different thicknesses than each other	
H10W  90/20		ؤ줿åפ֡Σ	Configurations of stacked chips	
H10W  90/22		åפѥåġ󥿡ݡޤϣңģ̤ξ̤Ȳ̤ξˤΡΣ	the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL	
H10W  90/24		ؤ줿åפξʤȤ⣱Ĥܤåפʿ˥եåȤƤΡ㡥ʾΤΡΣ	at least one of the stacked chips being laterally offset from a neighbouring stacked chip, e.g. chip stacks having a staircase shape	
H10W  90/26		ƱΥåפؤ졢Υåפʿ˥եåȤʤΡ㡥ĹΤΡΣ	the stacked chips being of the same size without any chips being laterally offset, e.g. chip stacks having a rectangular shape	
H10W  90/28		ۤʤ륵Υåפؤ줿Ρ㡥ԥߥåɷΤΡΣ	the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape	
H10W  95/00		Υ֥饹¾Υ롼פޤʤѥåˡΣ	Packaging processes not covered by the other groups of this subclass	
H10W  99/00		Υ֥饹¾Υ롼פޤʤΣ	Subject matter not provided for in other groups of this subclass	
